![STM32F410TBY6TR (WLCSP-36) — Figure 5. LQFP48 pinout [LQFP-48(7x7)]](/api/v1/assets/C5269948/extracted/figures/p32_fig01.png)
![STM32F410TBY6TR (WLCSP-36) — Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package [LQFP-48(7x7)]](/api/v1/assets/C5269948/extracted/figures/p127_fig01.png)
WLCSP-36 · 36P
Synchronized Pinout (Symbol / 2D / 3D) (36/36)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| A1 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| A2 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, SWD/JTAG) |
| A3 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C) |
| A4 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (SPI, I2C) |
| A5 | VSS | GND | Ground Reference Pin (VSS) |
| A6 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| B1 | VSS | GND | Ground Reference Pin (VSS) |
| B2 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (SWD/JTAG) |
| B3 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART, I2C) |
| B4 | PDR_ON | I/O | Multiplexed I/O & Peripheral Pin PDR_ON (General) |
| B5 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| B6 | PC14 - OSC32_IN | I/O | Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK) |
| C1 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (SWD/JTAG) |
| C2 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (UART, SPI, I2C, SWD/JTAG) |
| C3 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (UART, I2C) |
| C4 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| C5 | PH0 OSC IN -_ | I/O | Multiplexed I/O & Peripheral Pin PH0 OSC IN -_ (RTC/CLK) |
| C6 | PC15 - OSC32_OUT | I/O | Multiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK) |
| D1 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (UART, I2C, RTC/CLK) |
| D2 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (UART, SPI) |
| D3 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (SPI) |
| D4 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| D5 | NRST | I | System Enable & Hardware Reset (NRST) |
| D6 | PH1 - OSC_OUT | I/O | Multiplexed I/O & Peripheral Pin PH1 - OSC_OUT (RTC/CLK) |
| E1 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (SPI, I2C, PWM) |
| E2 | VCAP_1 | I/O | Multiplexed I/O & Peripheral Pin VCAP_1 (General) |
| E3 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (SPI, I2C) |
| E4 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM) |
| E5 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM) |
| E6 | VSSA/VREF - | GND | Ground Reference Pin (VSSA/VREF -) |
| F1 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| F2 | VSS | GND | Ground Reference Pin (VSS) |
| F3 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (General) |
| F4 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC) |
| F5 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM) |
| F6 | VDDA/VREF+ | Power | Power Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V)) |
PIN A1 VDD
PowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 20 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (36 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
WLCSP-36 · 2.60×2.60mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (36 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (20 figures · Page 1/2)
Showing 1–12 of 20 uncropped original figures for STM32F410
P34 · p34_fig01EXACT PACKAGE
P119 · p119_fig01EXACT PACKAGE
P120 · p120_fig01EXACT PACKAGE
P121 · p121_fig01EXACT PACKAGE
P1 · p01_fig01881×460px
P1 · p01_fig02883×372px
P50 · p50_fig011546×1214px
P81 · p81_fig011546×527px
P133 · p133_fig011548×639px
P133 · p133_fig021546×1139px
P32 · p32_fig01EXACT PACKAGE
P127 · p127_fig01EXACT PACKAGE
Page 1 / 2 (20 extracted figures)
Technical Specifications & Part Details (STM32F410TBY6TR)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32F410TBY6TR (WLCSP-36) is a 36-pin embedded microcontroller unit (mcu) featuring a 2.60 × 2.60 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
100 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
23 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.60 × 2.60 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-36)
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol36 auto-grouped pins
IPC-7351B Land Pattern36 pads · Pitch 0.40mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32F410 (15)
WLCSP-36(2.6x2.6) · 36P
WLCSP-36(2.6x2.6) · 36P
LQFP-48(7x7) · 48P
UFQFPN-48(7x7) · 49P
UFQFPN-48(7x7) · 49P
UFQFPN-48(7x7) · 49P
UFQFPN-48(7x7) · 49P
UFQFPN-48(7x7) · 49P
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
LQFP-48(7x7) · 36P
Mechanical Dimensions & Land Pattern (WLCSP-36)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
2.60 × 2.60 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
36P / 36Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit WLCSP-36 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32F410TBY6TR (WLCSP-36)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32F410TBY6TR (WLCSP-36)?
Manufactured by ST, the STM32F410TBY6TR is housed in a WLCSP-36 package with 36 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, SWD/JTAG)), A3 (PB5: Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C)), A4 (PB8: Multiplexed I/O & Peripheral Pin PB8 (SPI, I2C)), A5 (VSS: Ground Reference Pin (VSS)), A6 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))).
What are the IPC-7351B PCB Footprint dimensions for STM32F410TBY6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F410TBY6TR (WLCSP-36) has a nominal body envelope of 2.60 × 2.60 mm, pitch e = 0.40 mm, and 36 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F410TBY6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F410TBY6TR (ST, WLCSP-36) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (36 pins) & STM32F410 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A2 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| A3 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI. Supported peripheral buses: SPI, I2C. |
| A4 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, SPI5_MOSI. Supported peripheral buses: SPI, I2C. |
| A5 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A6 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| B1 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| B2 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG. |
| B3 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C. |
| B4 | PDR_ON | Digital_IO | Signal terminal PDR_ON (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General. |
| B5 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| B6 | PC14 - OSC32_IN | Digital_IO | Signal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK. |
| C1 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG. |
| C2 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SDA, SPI1_SCK, I2C2_SDA. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG. |
| C3 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C. |
| C4 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| C5 | PH0 OSC IN -_ | Digital_IO | Signal terminal PH0 OSC IN -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 OSC IN -_. Supported peripheral buses: RTC/CLK. |
| C6 | PC15 - OSC32_OUT | Digital_IO | Signal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| D1 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SCL. Supported peripheral buses: UART, I2C, RTC/CLK. |
| D2 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_MISO. Supported peripheral buses: UART, SPI. |
| D3 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI. |
| D4 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| D5 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| D6 | PH1 - OSC_OUT | Digital_IO | Signal terminal PH1 - OSC_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_OUT. Supported peripheral buses: RTC/CLK. |
| E1 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, SPI2_NSS. Supported peripheral buses: SPI, I2C, PWM. |
| E2 | VCAP_1 | Digital_IO | Signal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General. |
| E3 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, SPI2_SCK, I2C4_SCL. Supported peripheral buses: SPI, I2C. |
| E4 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM. |
| E5 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM. |
| E6 | VSSA/VREF - | GND | 0V electrical ground return terminal (VSSA/VREF -) for internal core logic, I/O drivers, and analog sub-blocks. |
| F1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| F2 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| F3 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| F4 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC. |
| F5 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM. |
| F6 | VDDA/VREF+ | Power_In | Primary positive power supply input (VDDA/VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |