![STM32L162ZET6 (LQFP-144(20x20)) — Figure 5. STM32L162RC LQFP64 pinout VDD_3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 [LQFP-64(10x10)]](/api/v1/assets/C1344302/extracted/figures/p34_fig01.png)
![STM32L162ZET6 (LQFP-144(20x20)) — Figure 32. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline SEATING PLANE C [LQFP-64(10x10)]](/api/v1/assets/C1344302/extracted/figures/p108_fig01.png)
![STM32L162ZET6 (LQFP-144(20x20)) — Figure 33. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package [LQFP-64(10x10)]](/api/v1/assets/C1344302/extracted/figures/p109_fig01.png)
LQFP-64(10x10) · 64P
Synchronized Pinout (Symbol / 2D / 3D) (144/144)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PE2 | I/O | Multiplexed I/O & Peripheral Pin PE2 (General) |
| 2 | PE3 | I/O | Multiplexed I/O & Peripheral Pin PE3 (General) |
| 3 | PE4 | I/O | Multiplexed I/O & Peripheral Pin PE4 (General) |
| 4 | PE5 | I/O | Multiplexed I/O & Peripheral Pin PE5 (General) |
| 5 | PE6 - WKUP3 | I/O | Multiplexed I/O & Peripheral Pin PE6 - WKUP3 (RTC/CLK) |
| 6 | V LCD | I/O | Multiplexed I/O & Peripheral Pin V LCD (General) |
| 7 | PC13 WKUP2 - | I/O | Multiplexed I/O & Peripheral Pin PC13 WKUP2 - (RTC/CLK) |
| 8 | PC14 - OSC32 IN(3)_ | I/O | Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(3)_ (RTC/CLK) |
| 9 | PC15 - OSC32_OUT | I/O | Multiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK) |
| 10 | PF0 | I/O | Multiplexed I/O & Peripheral Pin PF0 (General) |
| 11 | PF1 | I/O | Multiplexed I/O & Peripheral Pin PF1 (General) |
| 12 | PF2 | I/O | Multiplexed I/O & Peripheral Pin PF2 (General) |
| 13 | PF3 | I/O | Multiplexed I/O & Peripheral Pin PF3 (General) |
| 14 | PF4 | I/O | Multiplexed I/O & Peripheral Pin PF4 (General) |
| 15 | PF5 | I/O | Multiplexed I/O & Peripheral Pin PF5 (General) |
| 16 | VSS_5 | GND | Ground Reference Pin (VSS_5) |
| 17 | VDD_5 | Power | Power Supply Input (VDD_5 — 3.3V VDD (Max 4.0V)) |
| 18 | PF6 | I/O | Multiplexed I/O & Peripheral Pin PF6 (ADC) |
| 19 | PF7 | I/O | Multiplexed I/O & Peripheral Pin PF7 (ADC, PWM) |
| 20 | PF8 | I/O | Multiplexed I/O & Peripheral Pin PF8 (ADC, PWM) |
| 21 | PF9 | I/O | Multiplexed I/O & Peripheral Pin PF9 (ADC, PWM) |
| 22 | PF10 | I/O | Multiplexed I/O & Peripheral Pin PF10 (ADC) |
| 23 | PH0OSC IN(4) -_ | I/O | Multiplexed I/O & Peripheral Pin PH0OSC IN(4) -_ (RTC/CLK) |
| 24 | PH1 - OSC OUT(4)_ | I/O | Multiplexed I/O & Peripheral Pin PH1 - OSC OUT(4)_ (RTC/CLK) |
| 25 | NRST | I | System Enable & Hardware Reset (NRST) |
| 26 | PC0 | I/O | Multiplexed I/O & Peripheral Pin PC0 (ADC) |
| 27 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (ADC) |
| 28 | PC2 | I/O | Multiplexed I/O & Peripheral Pin PC2 (ADC) |
| 29 | PC3 | I/O | Multiplexed I/O & Peripheral Pin PC3 (ADC) |
| 30 | VSSA | GND | Ground Reference Pin (VSSA) |
| 31 | VREF- | Analog | Multiplexed I/O & Peripheral Pin VREF- (General) |
| 32 | VREF+ | Analog | Multiplexed I/O & Peripheral Pin VREF+ (General) |
| 33 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| 34 | PA0WKUP1 - | I/O | Multiplexed I/O & Peripheral Pin PA0WKUP1 - (UART, ADC, RTC/CLK) |
| 35 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, ADC) |
| 36 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, ADC) |
| 37 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (UART, ADC) |
| 38 | VSS_4 | GND | Ground Reference Pin (VSS_4) |
| 39 | VDD_4 | Power | Power Supply Input (VDD_4 — 3.3V VDD (Max 4.0V)) |
| 40 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC) |
| 41 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC) |
| 42 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC) |
| 43 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC) |
| 44 | PC4 | I/O | Multiplexed I/O & Peripheral Pin PC4 (ADC) |
| 45 | PC5 | I/O | Multiplexed I/O & Peripheral Pin PC5 (ADC) |
| 46 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (ADC) |
| 47 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (ADC) |
| 48 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (ADC) |
| 49 | PF11 | I/O | Multiplexed I/O & Peripheral Pin PF11 (ADC) |
| 50 | PF12 | I/O | Multiplexed I/O & Peripheral Pin PF12 (ADC) |
| 51 | VSS_6 | GND | Ground Reference Pin (VSS_6) |
| 52 | VDD_6 | Power | Power Supply Input (VDD_6 — 3.3V VDD (Max 4.0V)) |
| 53 | PF13 | I/O | Multiplexed I/O & Peripheral Pin PF13 (ADC) |
| 54 | PF14 | I/O | Multiplexed I/O & Peripheral Pin PF14 (ADC) |
| 55 | PF15 | I/O | Multiplexed I/O & Peripheral Pin PF15 (ADC) |
| 56 | PG0 | I/O | Multiplexed I/O & Peripheral Pin PG0 (ADC) |
| 57 | PG1 | I/O | Multiplexed I/O & Peripheral Pin PG1 (ADC) |
| 58 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (ADC) |
| 59 | PE8 | I/O | Multiplexed I/O & Peripheral Pin PE8 (ADC) |
| 60 | PE9 | I/O | Multiplexed I/O & Peripheral Pin PE9 (ADC, PWM) |
| 61 | VSS_7 | GND | Ground Reference Pin (VSS_7) |
| 62 | VDD_7 | Power | Power Supply Input (VDD_7 — 3.3V VDD (Max 4.0V)) |
| 63 | PE10 | I/O | Multiplexed I/O & Peripheral Pin PE10 (ADC, PWM) |
| 64 | PE11 | I/O | Multiplexed I/O & Peripheral Pin PE11 (PWM) |
| 65 | PE12 | I/O | Multiplexed I/O & Peripheral Pin PE12 (SPI) |
| 66 | PE13 | I/O | Multiplexed I/O & Peripheral Pin PE13 (SPI) |
| 67 | PE14 | I/O | Multiplexed I/O & Peripheral Pin PE14 (SPI) |
| 68 | PE15 | I/O | Multiplexed I/O & Peripheral Pin PE15 (SPI) |
| 69 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (UART, I2C) |
| 70 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (UART, I2C) |
| 71 | VSS_1 | GND | Ground Reference Pin (VSS_1) |
| 72 | VDD_1 | Power | Power Supply Input (VDD_1 — 3.3V VDD (Max 4.0V)) |
| 73 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, ADC) |
| 74 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, ADC) |
| 75 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (UART, SPI, ADC) |
| 76 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (SPI, ADC, RTC/CLK) |
| 77 | PD8 | I/O | Multiplexed I/O & Peripheral Pin PD8 (UART) |
| 78 | PD9 | I/O | Multiplexed I/O & Peripheral Pin PD9 (UART) |
| 79 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (UART) |
| 80 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (UART) |
| 81 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (UART) |
| 82 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (General) |
| 83 | VSS_8 | GND | Ground Reference Pin (VSS_8) |
| 84 | VDD_8 | Power | Power Supply Input (VDD_8 — 3.3V VDD (Max 4.0V)) |
| 85 | PD14 | I/O | Multiplexed I/O & Peripheral Pin PD14 (General) |
| 86 | PD15 | I/O | Multiplexed I/O & Peripheral Pin PD15 (General) |
| 87 | PG2 | I/O | Multiplexed I/O & Peripheral Pin PG2 (ADC) |
| 88 | PG3 | I/O | Multiplexed I/O & Peripheral Pin PG3 (ADC) |
| 89 | PG4 | I/O | Multiplexed I/O & Peripheral Pin PG4 (ADC) |
| 90 | PG5 | I/O | Multiplexed I/O & Peripheral Pin PG5 (General) |
| 91 | PG6 | I/O | Multiplexed I/O & Peripheral Pin PG6 (General) |
| 92 | PG7 | I/O | Multiplexed I/O & Peripheral Pin PG7 (General) |
| 93 | PG8 | I/O | Multiplexed I/O & Peripheral Pin PG8 (General) |
| 94 | VSS_9 | GND | Ground Reference Pin (VSS_9) |
| 95 | VDD_9 | Power | Power Supply Input (VDD_9 — 3.3V VDD (Max 4.0V)) |
| 96 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (General) |
| 97 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (General) |
| 98 | PC8 | I/O | Multiplexed I/O & Peripheral Pin PC8 (General) |
| 99 | PC9 | I/O | Multiplexed I/O & Peripheral Pin PC9 (General) |
| 100 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK) |
| 101 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (UART) |
| 102 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (UART) |
| 103 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI) |
| 104 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI) |
| 105 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (SWD/JTAG) |
| 106 | PH2 | I/O | Multiplexed I/O & Peripheral Pin PH2 (General) |
| 107 | VSS_2 | GND | Ground Reference Pin (VSS_2) |
| 108 | VDD_2 | Power | Power Supply Input (VDD_2 — 3.3V VDD (Max 4.0V)) |
| 109 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (SWD/JTAG) |
| 110 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG) |
| 111 | PC10 | I/O | Multiplexed I/O & Peripheral Pin PC10 (UART, SPI) |
| 112 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (UART, SPI) |
| 113 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (UART, SPI) |
| 114 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (SPI) |
| 115 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (SPI) |
| 116 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (UART) |
| 117 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (UART, SPI) |
| 118 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (UART, SPI) |
| 119 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (UART) |
| 120 | VSS_10 | GND | Ground Reference Pin (VSS_10) |
| 121 | VDD_10 | Power | Power Supply Input (VDD_10 — 3.3V VDD (Max 4.0V)) |
| 122 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (UART) |
| 123 | PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 (UART) |
| 124 | PG9 | I/O | Multiplexed I/O & Peripheral Pin PG9 (General) |
| 125 | PG10 | I/O | Multiplexed I/O & Peripheral Pin PG10 (General) |
| 126 | PG11 | I/O | Multiplexed I/O & Peripheral Pin PG11 (General) |
| 127 | PG12 | I/O | Multiplexed I/O & Peripheral Pin PG12 (General) |
| 128 | PG13 | I/O | Multiplexed I/O & Peripheral Pin PG13 (General) |
| 129 | PG14 | I/O | Multiplexed I/O & Peripheral Pin PG14 (General) |
| 130 | VSS_11 | GND | Ground Reference Pin (VSS_11) |
| 131 | VDD_11 | Power | Power Supply Input (VDD_11 — 3.3V VDD (Max 4.0V)) |
| 132 | PG15 | I/O | Multiplexed I/O & Peripheral Pin PG15 (General) |
| 133 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG) |
| 134 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG) |
| 135 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C) |
| 136 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART, I2C) |
| 137 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (UART, I2C) |
| 138 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| 139 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (I2C) |
| 140 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (I2C) |
| 141 | PE0 | I/O | Multiplexed I/O & Peripheral Pin PE0 (General) |
| 142 | PE1 | I/O | Multiplexed I/O & Peripheral Pin PE1 (General) |
| 143 | VSS_3 | GND | Ground Reference Pin (VSS_3) |
| 144 | VDD_3 | Power | Power Supply Input (VDD_3 — 3.3V VDD (Max 4.0V)) |
PIN 1 PE2
I/OMultiplexed I/O & Peripheral Pin PE2 (General)
Design note: PE2 | Alt: TIM3 ETR/LCD SEG38/__ TRACECLK
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 34 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-144(20x20) · 20.00×20.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (34 figures · Page 1/3)
Showing 1–12 of 34 uncropped original figures for STM32L162
P1 · p01_fig02EXACT PACKAGE
P31 · p31_fig01EXACT PACKAGE
P113 · p113_fig01EXACT PACKAGE
P115 · p115_fig01EXACT PACKAGE
P115 · p115_fig02EXACT PACKAGE
P1 · p01_fig01881×467px
P79 · p79_fig011546×548px
P123 · p123_fig011542×668px
P128 · p128_fig011548×2026px
P34 · p34_fig01EXACT PACKAGE
P108 · p108_fig01EXACT PACKAGE
P109 · p109_fig01EXACT PACKAGE
Page 1 / 3 (34 extracted figures)
Technical Specifications & Part Details (STM32L162ZET6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32L162ZET6 (LQFP-144(20x20)) is a 144-pin embedded microcontroller unit (mcu) featuring a 20.00 × 20.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.65 V to 3.6 V supply operation across -40 °C to 105 °C with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40 °C to 105 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
102 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
20.00 × 20.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-144(20x20))
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol144 auto-grouped pins
IPC-7351B Land Pattern144 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32L162 (15)
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
WLCSP-64(4.5x4.9) · 64P
BGA-100 · 100P
LQFP-100(14x14) · 100P
WLCSP-104(4.1x5.1) · 104P
IPC-7351B
104P5.1×4.1×0.55mmP=0.4mm
STM32L162 (WLCSP-104(4.1x5.1))
WLCSP-104(4.1x5.1) · 104P
IPC-7351B
104P5.1×4.1×0.56mmP=0.4mm
STM32L162 (WLCSP-104(4.1x5.1))
BGA-132 · 132P
BGA-132 · 132P
UFBGA-132 · 132P
UFBGA-132 · 132P
LQFP-144(20x20) · 144P
LQFP-144(20x20) · 144P
Mechanical Dimensions & Land Pattern (LQFP-144(20x20))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.27 × 1.30 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-144(20x20) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32L162ZET6 (LQFP-144(20x20))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32L162ZET6 (LQFP-144(20x20))?
Manufactured by ST, the STM32L162ZET6 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6 - WKUP3: Multiplexed I/O & Peripheral Pin PE6 - WKUP3 (RTC/CLK)), 6 (V LCD: Multiplexed I/O & Peripheral Pin V LCD (General)).
What are the IPC-7351B PCB Footprint dimensions for STM32L162ZET6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L162ZET6 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L162ZET6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L162ZET6 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (144 pins) & STM32L162 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| 2 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| 3 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| 4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General. |
| 5 | PE6 - WKUP3 | Digital_IO | Signal terminal PE6 - WKUP3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6 - WKUP3. Supported peripheral buses: RTC/CLK. |
| 6 | V LCD | Digital_IO | Signal terminal V LCD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V LCD. Supported peripheral buses: General. |
| 7 | PC13 WKUP2 - | Digital_IO | Signal terminal PC13 WKUP2 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13 WKUP2 -. Supported peripheral buses: RTC/CLK. |
| 8 | PC14 - OSC32 IN(3)_ | Digital_IO | Signal terminal PC14 - OSC32 IN(3)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32 IN(3)_. Supported peripheral buses: RTC/CLK. |
| 9 | PC15 - OSC32_OUT | Digital_IO | Signal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| 10 | PF0 | Digital_IO | Signal terminal PF0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General. |
| 11 | PF1 | Digital_IO | Signal terminal PF1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General. |
| 12 | PF2 | Digital_IO | Signal terminal PF2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General. |
| 13 | PF3 | Digital_IO | Signal terminal PF3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General. |
| 14 | PF4 | Digital_IO | Signal terminal PF4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General. |
| 15 | PF5 | Digital_IO | Signal terminal PF5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General. |
| 16 | VSS_5 | GND | 0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks. |
| 17 | VDD_5 | Power_In | Primary positive power supply input (VDD_5) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 18 | PF6 | Digital_IO | Signal terminal PF6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: ADC. |
| 19 | PF7 | Digital_IO | Signal terminal PF7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: ADC, PWM. |
| 20 | PF8 | Digital_IO | Signal terminal PF8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF8. Supported peripheral buses: ADC, PWM. |
| 21 | PF9 | Digital_IO | Signal terminal PF9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF9. Supported peripheral buses: ADC, PWM. |
| 22 | PF10 | Digital_IO | Signal terminal PF10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: ADC. |
| 23 | PH0OSC IN(4) -_ | Digital_IO | Signal terminal PH0OSC IN(4) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN(4) -_. Supported peripheral buses: RTC/CLK. |
| 24 | PH1 - OSC OUT(4)_ | Digital_IO | Signal terminal PH1 - OSC OUT(4)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1 - OSC OUT(4)_. Supported peripheral buses: RTC/CLK. |
| 25 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 26 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC. |
| 27 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC. |
| 28 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC. |
| 29 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC. |
| 30 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 31 | VREF- | Analog | Signal terminal VREF- (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General. |
| 32 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 33 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 34 | PA0WKUP1 - | Digital_IO | Signal terminal PA0WKUP1 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0WKUP1 -. Supported peripheral buses: UART, ADC, RTC/CLK. |
| 35 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC. |
| 36 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC. |
| 37 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC. |
| 38 | VSS_4 | GND | 0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks. |
| 39 | VDD_4 | Power_In | Primary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 40 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC. |
| 41 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC. |
| 42 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC. |
| 43 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC. |
| 44 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC. |
| 45 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC. |
| 46 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC. |
| 47 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC. |
| 48 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: ADC. |
| 49 | PF11 | Digital_IO | Signal terminal PF11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF11. Supported peripheral buses: ADC. |
| 50 | PF12 | Digital_IO | Signal terminal PF12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: ADC. |
| 51 | VSS_6 | GND | 0V electrical ground return terminal (VSS_6) for internal core logic, I/O drivers, and analog sub-blocks. |
| 52 | VDD_6 | Power_In | Primary positive power supply input (VDD_6) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 53 | PF13 | Digital_IO | Signal terminal PF13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: ADC. |
| 54 | PF14 | Digital_IO | Signal terminal PF14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: ADC. |
| 55 | PF15 | Digital_IO | Signal terminal PF15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF15. Supported peripheral buses: ADC. |
| 56 | PG0 | Digital_IO | Signal terminal PG0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG0. Supported peripheral buses: ADC. |
| 57 | PG1 | Digital_IO | Signal terminal PG1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG1. Supported peripheral buses: ADC. |
| 58 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: ADC. |
| 59 | PE8 | Digital_IO | Signal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: ADC. |
| 60 | PE9 | Digital_IO | Signal terminal PE9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: ADC, PWM. |
| 61 | VSS_7 | GND | 0V electrical ground return terminal (VSS_7) for internal core logic, I/O drivers, and analog sub-blocks. |
| 62 | VDD_7 | Power_In | Primary positive power supply input (VDD_7) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 63 | PE10 | Digital_IO | Signal terminal PE10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: ADC, PWM. |
| 64 | PE11 | Digital_IO | Signal terminal PE11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: PWM. |