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STM32L162QDH6 (UFBGA-132) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L162QDH6

STID: C1342787UFBGA-132 · 132 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L162QDH6 (UFBGA-132)A1PE3A2PE1A3PB8A4BOOT0A5PD7A6PD5A7PB4A8PB3A9PA15A10PA14A11PA13A12PA12B1PE4B2PE2B3PB9B4PB7B5PB6B6PD6B7PD4B8PD3B9PD1B10PC12B11PC10B12PA11C1PC13WKUP2 -C2PE5C3PE0C4VDD_3C5PB5C6PG14C7PG13C8PD2C9PD0C10PC11C11PH2C12PA10D1PC14 - OSC32D2PE6 - WKUP3D3VSS_3D4PF2D5PF1D6PF0D7PG12D8PG10D9PG9D10PA9D11PA8D12PC9E1PC15 - OSC32E2V LCDE3VSS_6E4PF3E9PG5E10PC8E11PC7E12PC6F1PH0OSC IN(5)F2VSS_5F3PF4F4PF5F6VSS_9F7VSS_10F9PG3F10PG4F11VSS_2F12VSS_1M12PE15M11PE14M10PE13M9PE11M8PE9M7PE7M6PB1M5PB0M4OPAMP2_VINMM3OPAMP1_VINMM2PA1M1VDDAL12PB12L11PB11L10PB10L9PE12L8PE10L7PE8L6PB2L5PC5L4PA6L3PA3L2PA0WKUP1 -L1VREF+K12PB13K11PB14K10PB15K9PD8K8PD9K7PF13K6PF11K5PC4K4PA5K3PA2K2PC3K1OPAMP3_VINMJ12PD10J11PD11J10PD12J9PF15J8PF14J7PF12J6PF9J5PA7J4PA4J3PC2J2PC1J1VSSAH12PD13H11PD14H10PD15H9PG0H4PF8H3VDD_6H2NRSTH1PC0G12VDD_1G11VDD_2G10PG2G9PG1G7VDD_10G6VDD_9G4PF7G3PF6G2VDD_5G1PH1 - OSC OUGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.888.983.878.773.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7-78.7-83.8-88.9mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10A11A12B1B2B3B4B5B6B7B8B9B10B11B12C1C2C3C4C5C6C7C8C9C10C11C12D1D2D3D4D5D6D7D8D9D10D11D12E1E2E3E4E9E10E11E12F1F2F3F4F6F7F9F10F11F12G1G2G3G4G6G7G9G10G11G12H1H2H3H4H9H10H11H12J1J2J3J4J5J6J7J8J9J10J11J12K1K2K3K4K5K6K7K8K9K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12M1M2M3M4M5M6M7M8M9M10M11M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (132/132)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A2PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
A4BOOT0IInput-Only Pin BOOT0 (General)
A5PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
A6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
A7PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
A8PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
A9PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
A10PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
A11PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
A12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI)
B1PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B2PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
B3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
B4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART)
B7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, SPI)
B8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
B9PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI)
B10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI)
C1PC13WKUP2 -I/OMultiplexed I/O & Peripheral Pin PC13WKUP2 - (RTC/CLK)
C2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
C3PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C4VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
C6PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
C7PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
C8PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
C9PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI)
C10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C11PH2I/OMultiplexed I/O & Peripheral Pin PH2 (General)
C12PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
D1PC14 - OSC32 IN(4)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(4)_ (RTC/CLK)
D2PE6 - WKUP3I/OMultiplexed I/O & Peripheral Pin PE6 - WKUP3 (RTC/CLK)
D3VSS_3GNDGround Reference Pin (VSS_3)
D4PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
D5PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
D6PF0I/OMultiplexed I/O & Peripheral Pin PF0 (General)
D7PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
D8PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
D9PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
D10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
D11PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D12PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E1PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
E2V LCDI/OMultiplexed I/O & Peripheral Pin V LCD (General)
E3VSS_6GNDGround Reference Pin (VSS_6)
E4PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
E9PG5I/OMultiplexed I/O & Peripheral Pin PG5 (General)
E10PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
E11PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F1PH0OSC IN(5) -_I/OMultiplexed I/O & Peripheral Pin PH0OSC IN(5) -_ (RTC/CLK)
F2VSS_5GNDGround Reference Pin (VSS_5)
F3PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
F4PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
F6VSS_9GNDGround Reference Pin (VSS_9)
F7VSS_10GNDGround Reference Pin (VSS_10)
F9PG3I/OMultiplexed I/O & Peripheral Pin PG3 (ADC)
F10PG4I/OMultiplexed I/O & Peripheral Pin PG4 (ADC)
F11VSS_2GNDGround Reference Pin (VSS_2)
F12VSS_1GNDGround Reference Pin (VSS_1)
G1PH1 - OSC OUT(5)_I/OMultiplexed I/O & Peripheral Pin PH1 - OSC OUT(5)_ (RTC/CLK)
G2VDD_5PowerPower Supply Input (VDD_5 — 3.3V VDD (Max 4.0V))
G3PF6I/OMultiplexed I/O & Peripheral Pin PF6 (ADC)
G4PF7I/OMultiplexed I/O & Peripheral Pin PF7 (ADC, PWM)
G6VDD_9PowerPower Supply Input (VDD_9 — 3.3V VDD (Max 4.0V))
G7VDD_10PowerPower Supply Input (VDD_10 — 3.3V VDD (Max 4.0V))
G9PG1I/OMultiplexed I/O & Peripheral Pin PG1 (ADC)
G10PG2I/OMultiplexed I/O & Peripheral Pin PG2 (ADC)
G11VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
G12VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
H1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H2NRSTISystem Enable & Hardware Reset (NRST)
H3VDD_6PowerPower Supply Input (VDD_6 — 3.3V VDD (Max 4.0V))
H4PF8I/OMultiplexed I/O & Peripheral Pin PF8 (ADC, PWM)
H9PG0I/OMultiplexed I/O & Peripheral Pin PG0 (ADC)
H10PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
H11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
H12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
J1VSSAGNDGround Reference Pin (VSSA)
J2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
J3PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
J4PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
J5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
J6PF9I/OMultiplexed I/O & Peripheral Pin PF9 (ADC, PWM)
J7PF12I/OMultiplexed I/O & Peripheral Pin PF12 (ADC)
J8PF14I/OMultiplexed I/O & Peripheral Pin PF14 (ADC)
J9PF15I/OMultiplexed I/O & Peripheral Pin PF15 (ADC)
J10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, PWM)
J11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART)
J12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
K1OPAMP3_VINMPowerPower Supply Input (OPAMP3_VINM — 3.3V VDD (Max 4.0V))
K2PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
K3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
K4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
K5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
K6PF11I/OMultiplexed I/O & Peripheral Pin PF11 (ADC)
K7PF13I/OMultiplexed I/O & Peripheral Pin PF13 (ADC)
K8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
K9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
K10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, ADC, RTC/CLK)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, ADC)
K12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, ADC)
L1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
L2PA0WKUP1 -I/OMultiplexed I/O & Peripheral Pin PA0WKUP1 - (UART, ADC, RTC/CLK)
L3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
L4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
L5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
L6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (ADC)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (ADC)
L8PE10I/OMultiplexed I/O & Peripheral Pin PE10 (ADC)
L9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (SPI)
L10PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
L11PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
L12PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, ADC)
M1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
M2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
M3OPAMP1_VINMPowerPower Supply Input (OPAMP1_VINM — 3.3V VDD (Max 4.0V))
M4OPAMP2_VINMPowerPower Supply Input (OPAMP2_VINM — 3.3V VDD (Max 4.0V))
M5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC)
M6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (ADC)
M8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (ADC, PWM)
M9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
M10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (SPI)
M11PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI)
M12PE15I/OMultiplexed I/O & Peripheral Pin PE15 (SPI)
PIN A1 PE3
I/O
Multiplexed I/O & Peripheral Pin PE3 (General)
Design note: PE3 | Alt: TIM3 CH1/LCD SEG39/__ FSMC A19/TRACED0_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L162QDH6 (ST · UFBGA-132)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L162QDH6 (UFBGA-132) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L162QDH6 (UFBGA-132) - 2. Standard Pinout (Top View)
True package pinout (132 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L162QDH6 (UFBGA-132) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L162QDH6 (UFBGA-132) - 4. Package Dimensions (D×E×A)
UFBGA-132 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L162QDH6 (UFBGA-132) - 5. Recommended Land Pattern
IPC-7351B Footprint (132 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L162QDH6 (UFBGA-132) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for STM32L162
P1 · p01_fig01EXACT PACKAGE
STM32L162QDH6 (UFBGA-132) — • AES-128 bit encryption hardware accelerator
• AES-128 bit encryption hardware accelerator
P36 · p36_fig01EXACT PACKAGE
STM32L162QDH6 (UFBGA-132) — Figure 4. STM32L162QD UFBGA132 ballout
Figure 4. STM32L162QD UFBGA132 ballout
P140 · p140_fig01EXACT PACKAGE
STM32L162QDH6 (UFBGA-132) — Figure 49. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
Figure 49. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
P141 · p141_fig01EXACT PACKAGE
STM32L162QDH6 (UFBGA-132) — Figure 50. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
Figure 50. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
P152 · p152_fig01EXACT PACKAGE
STM32L162QDH6 (UFBGA-132) — Revision History STM32L162VD STM32L162ZD STM32L162QD STM32L162RD
Revision History STM32L162VD STM32L162ZD STM32L162QD STM32L162RD
P60 · p60_fig011546×1260px
STM32L162QDH6 (UFBGA-132) — Figure 11. Power supply scheme
Figure 11. Power supply scheme
P60 · p60_fig01P60
STM32L162QDH6 (UFBGA-132) — Datasheet Page 60 (p60_fig01)
Datasheet Page 60 (p60_fig01)
P61 · p61_fig011546×702px
STM32L162QDH6 (UFBGA-132) — Figure 12. Optional LCD power supply scheme
Figure 12. Optional LCD power supply scheme
P61 · p61_fig021546×814px
STM32L162QDH6 (UFBGA-132) — Figure 13. Current consumption measurement scheme
Figure 13. Current consumption measurement scheme
P84 · p84_fig011546×548px
STM32L162QDH6 (UFBGA-132) — Figure 17. Typical application with a 32.768 kHz crystal
Figure 17. Typical application with a 32.768 kHz crystal
P144 · p144_fig011548×1064px
STM32L162QDH6 (UFBGA-132) — Figure 53. WLCSP64, 0.4 mm pitch wafer level chip scale package
Figure 53. WLCSP64, 0.4 mm pitch wafer level chip scale package

Technical Specifications & Part Details (STM32L162QDH6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L162QDH6 (UFBGA-132) is a 132-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.53 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C to 105°C with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 105°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-132)
Pin Count & Lead PitchN / e
132 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol132 auto-grouped pins
OK
IPC-7351B Land Pattern132 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-132)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
132P / 132Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-132
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L162QDH6 (UFBGA-132)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L162QDH6 (UFBGA-132)?

Manufactured by ST, the STM32L162QDH6 is housed in a UFBGA-132 package with 132 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: A1 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A2 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A3 (PB8: Multiplexed I/O & Peripheral Pin PB8 (I2C)), A4 (BOOT0: Input-Only Pin BOOT0 (General)), A5 (PD7: Multiplexed I/O & Peripheral Pin PD7 (UART)), A6 (PD5: Multiplexed I/O & Peripheral Pin PD5 (UART)).

What are the IPC-7351B PCB Footprint dimensions for STM32L162QDH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L162QDH6 (UFBGA-132) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 132 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L162QDH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L162QDH6 (ST, UFBGA-132) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (132 pins) & STM32L162 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A2PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
A4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A5PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
A6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
A7PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_MISO. Supported peripheral buses: SPI, SWD/JTAG.
A8PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: SPI, SWD/JTAG.
A9PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
A10PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
A11PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
A12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI, USB_DP. Supported peripheral buses: USB, UART, SPI.
B1PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B2PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
B3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
B4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
B6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART.
B7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
B8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI.
B9PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI.
B10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
B12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO, USB_DM. Supported peripheral buses: USB, UART, SPI.
C1PC13WKUP2 -Digital_IOSignal terminal PC13WKUP2 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13WKUP2 -. Supported peripheral buses: RTC/CLK.
C2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
C3PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C4VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: SPI, I2C.
C6PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General.
C7PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General.
C8PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
C9PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI.
C10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI.
C11PH2Digital_IOSignal terminal PH2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH2. Supported peripheral buses: General.
C12PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
D1PC14 - OSC32 IN(4)_Digital_IOSignal terminal PC14 - OSC32 IN(4)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32 IN(4)_. Supported peripheral buses: RTC/CLK.
D2PE6 - WKUP3Digital_IOSignal terminal PE6 - WKUP3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6 - WKUP3. Supported peripheral buses: RTC/CLK.
D3VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
D4PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
D5PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
D6PF0Digital_IOSignal terminal PF0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
D7PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General.
D8PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General.
D9PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General.
D10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
D11PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D12PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E1PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
E2V LCDDigital_IOSignal terminal V LCD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V LCD. Supported peripheral buses: General.
E3VSS_6GND0V electrical ground return terminal (VSS_6) for internal core logic, I/O drivers, and analog sub-blocks.
E4PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
E9PG5Digital_IOSignal terminal PG5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG5. Supported peripheral buses: General.
E10PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
E11PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E12PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F1PH0OSC IN(5) -_Digital_IOSignal terminal PH0OSC IN(5) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN(5) -_. Supported peripheral buses: RTC/CLK.
F2VSS_5GND0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
F3PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
F4PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
F6VSS_9GND0V electrical ground return terminal (VSS_9) for internal core logic, I/O drivers, and analog sub-blocks.
F7VSS_10GND0V electrical ground return terminal (VSS_10) for internal core logic, I/O drivers, and analog sub-blocks.
F9PG3Digital_IOSignal terminal PG3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG3. Supported peripheral buses: ADC.
F10PG4Digital_IOSignal terminal PG4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG4. Supported peripheral buses: ADC.
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