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CH9130L (LQFP-128(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9130L

WCHID: C97380LQFP-128(14x14) · 128 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9130L (LQFP-128(14x14))1P12P23P34P45P56P67P78P89P910P1011P1112P1213P1314P1415P1516P1617P1718P1819P1920P2021P2122P2223P2324P2425P2526P2627P2728P2829P2930P3031P3132P3233P3334P3435P3536P3637P3738P3839P3940P4041P4142P4243P4344P4445P4546P4647P4748P4849P4950P5051P5152P5253P5354P5455P5556P5657P5758P5859P5960P6061P6162P6263P6364P64128P128127P127126P126125P125124P124123P123122P122121P121120P120119P119118P118117P117116P116115P115114P114113P113112P112111P111110P110109P109108P108107P107106P106105P105104P104103P103102P102101P101100P10099P9998P9897P9796P9695P9594P9493P9392P9291P9190P9089P8988P8887P8786P8685P8584P8483P8382P8281P8180P8079P7978P7877P7776P7675P7574P7473P7372P7271P7170P7069P6968P6867P6766P6665P65Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.286.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128E=14.00mm · Pitch e=0.40mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (128/128)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P1I/OMultiplexed I/O & Peripheral Pin P1 (General)
2P2I/OMultiplexed I/O & Peripheral Pin P2 (General)
3P3I/OMultiplexed I/O & Peripheral Pin P3 (General)
4P4I/OMultiplexed I/O & Peripheral Pin P4 (General)
5P5I/OMultiplexed I/O & Peripheral Pin P5 (General)
6P6I/OMultiplexed I/O & Peripheral Pin P6 (General)
7P7I/OMultiplexed I/O & Peripheral Pin P7 (General)
8P8I/OMultiplexed I/O & Peripheral Pin P8 (General)
9P9I/OMultiplexed I/O & Peripheral Pin P9 (General)
10P10I/OMultiplexed I/O & Peripheral Pin P10 (General)
11P11I/OMultiplexed I/O & Peripheral Pin P11 (General)
12P12I/OMultiplexed I/O & Peripheral Pin P12 (General)
13P13I/OMultiplexed I/O & Peripheral Pin P13 (General)
14P14I/OMultiplexed I/O & Peripheral Pin P14 (General)
15P15I/OMultiplexed I/O & Peripheral Pin P15 (General)
16P16I/OMultiplexed I/O & Peripheral Pin P16 (General)
17P17I/OMultiplexed I/O & Peripheral Pin P17 (General)
18P18I/OMultiplexed I/O & Peripheral Pin P18 (General)
19P19I/OMultiplexed I/O & Peripheral Pin P19 (General)
20P20I/OMultiplexed I/O & Peripheral Pin P20 (General)
21P21I/OMultiplexed I/O & Peripheral Pin P21 (General)
22P22I/OMultiplexed I/O & Peripheral Pin P22 (General)
23P23I/OMultiplexed I/O & Peripheral Pin P23 (General)
24P24I/OMultiplexed I/O & Peripheral Pin P24 (General)
25P25I/OMultiplexed I/O & Peripheral Pin P25 (General)
26P26I/OMultiplexed I/O & Peripheral Pin P26 (General)
27P27I/OMultiplexed I/O & Peripheral Pin P27 (General)
28P28I/OMultiplexed I/O & Peripheral Pin P28 (General)
29P29I/OMultiplexed I/O & Peripheral Pin P29 (General)
30P30I/OMultiplexed I/O & Peripheral Pin P30 (General)
31P31I/OMultiplexed I/O & Peripheral Pin P31 (General)
32P32I/OMultiplexed I/O & Peripheral Pin P32 (General)
33P33I/OSynthesized pin mapping for EDA symbol-footprint netlist
34P34I/OSynthesized pin mapping for EDA symbol-footprint netlist
35P35I/OSynthesized pin mapping for EDA symbol-footprint netlist
36P36I/OSynthesized pin mapping for EDA symbol-footprint netlist
37P37I/OSynthesized pin mapping for EDA symbol-footprint netlist
38P38I/OSynthesized pin mapping for EDA symbol-footprint netlist
39P39I/OSynthesized pin mapping for EDA symbol-footprint netlist
40P40I/OSynthesized pin mapping for EDA symbol-footprint netlist
41P41I/OSynthesized pin mapping for EDA symbol-footprint netlist
42P42I/OSynthesized pin mapping for EDA symbol-footprint netlist
43P43I/OSynthesized pin mapping for EDA symbol-footprint netlist
44P44I/OSynthesized pin mapping for EDA symbol-footprint netlist
45P45I/OSynthesized pin mapping for EDA symbol-footprint netlist
46P46I/OSynthesized pin mapping for EDA symbol-footprint netlist
47P47I/OSynthesized pin mapping for EDA symbol-footprint netlist
48P48I/OSynthesized pin mapping for EDA symbol-footprint netlist
49P49I/OSynthesized pin mapping for EDA symbol-footprint netlist
50P50I/OSynthesized pin mapping for EDA symbol-footprint netlist
51P51I/OSynthesized pin mapping for EDA symbol-footprint netlist
52P52I/OSynthesized pin mapping for EDA symbol-footprint netlist
53P53I/OSynthesized pin mapping for EDA symbol-footprint netlist
54P54I/OSynthesized pin mapping for EDA symbol-footprint netlist
55P55I/OSynthesized pin mapping for EDA symbol-footprint netlist
56P56I/OSynthesized pin mapping for EDA symbol-footprint netlist
57P57I/OSynthesized pin mapping for EDA symbol-footprint netlist
58P58I/OSynthesized pin mapping for EDA symbol-footprint netlist
59P59I/OSynthesized pin mapping for EDA symbol-footprint netlist
60P60I/OSynthesized pin mapping for EDA symbol-footprint netlist
61P61I/OSynthesized pin mapping for EDA symbol-footprint netlist
62P62I/OSynthesized pin mapping for EDA symbol-footprint netlist
63P63I/OSynthesized pin mapping for EDA symbol-footprint netlist
64P64I/OSynthesized pin mapping for EDA symbol-footprint netlist
65P65I/OSynthesized pin mapping for EDA symbol-footprint netlist
66P66I/OSynthesized pin mapping for EDA symbol-footprint netlist
67P67I/OSynthesized pin mapping for EDA symbol-footprint netlist
68P68I/OSynthesized pin mapping for EDA symbol-footprint netlist
69P69I/OSynthesized pin mapping for EDA symbol-footprint netlist
70P70I/OSynthesized pin mapping for EDA symbol-footprint netlist
71P71I/OSynthesized pin mapping for EDA symbol-footprint netlist
72P72I/OSynthesized pin mapping for EDA symbol-footprint netlist
73P73I/OSynthesized pin mapping for EDA symbol-footprint netlist
74P74I/OSynthesized pin mapping for EDA symbol-footprint netlist
75P75I/OSynthesized pin mapping for EDA symbol-footprint netlist
76P76I/OSynthesized pin mapping for EDA symbol-footprint netlist
77P77I/OSynthesized pin mapping for EDA symbol-footprint netlist
78P78I/OSynthesized pin mapping for EDA symbol-footprint netlist
79P79I/OSynthesized pin mapping for EDA symbol-footprint netlist
80P80I/OSynthesized pin mapping for EDA symbol-footprint netlist
81P81I/OSynthesized pin mapping for EDA symbol-footprint netlist
82P82I/OSynthesized pin mapping for EDA symbol-footprint netlist
83P83I/OSynthesized pin mapping for EDA symbol-footprint netlist
84P84I/OSynthesized pin mapping for EDA symbol-footprint netlist
85P85I/OSynthesized pin mapping for EDA symbol-footprint netlist
86P86I/OSynthesized pin mapping for EDA symbol-footprint netlist
87P87I/OSynthesized pin mapping for EDA symbol-footprint netlist
88P88I/OSynthesized pin mapping for EDA symbol-footprint netlist
89P89I/OSynthesized pin mapping for EDA symbol-footprint netlist
90P90I/OSynthesized pin mapping for EDA symbol-footprint netlist
91P91I/OSynthesized pin mapping for EDA symbol-footprint netlist
92P92I/OSynthesized pin mapping for EDA symbol-footprint netlist
93P93I/OSynthesized pin mapping for EDA symbol-footprint netlist
94P94I/OSynthesized pin mapping for EDA symbol-footprint netlist
95P95I/OSynthesized pin mapping for EDA symbol-footprint netlist
96P96I/OSynthesized pin mapping for EDA symbol-footprint netlist
97P97I/OSynthesized pin mapping for EDA symbol-footprint netlist
98P98I/OSynthesized pin mapping for EDA symbol-footprint netlist
99P99I/OSynthesized pin mapping for EDA symbol-footprint netlist
100P100I/OSynthesized pin mapping for EDA symbol-footprint netlist
101P101I/OSynthesized pin mapping for EDA symbol-footprint netlist
102P102I/OSynthesized pin mapping for EDA symbol-footprint netlist
103P103I/OSynthesized pin mapping for EDA symbol-footprint netlist
104P104I/OSynthesized pin mapping for EDA symbol-footprint netlist
105P105I/OSynthesized pin mapping for EDA symbol-footprint netlist
106P106I/OSynthesized pin mapping for EDA symbol-footprint netlist
107P107I/OSynthesized pin mapping for EDA symbol-footprint netlist
108P108I/OSynthesized pin mapping for EDA symbol-footprint netlist
109P109I/OSynthesized pin mapping for EDA symbol-footprint netlist
110P110I/OSynthesized pin mapping for EDA symbol-footprint netlist
111P111I/OSynthesized pin mapping for EDA symbol-footprint netlist
112P112I/OSynthesized pin mapping for EDA symbol-footprint netlist
113P113I/OSynthesized pin mapping for EDA symbol-footprint netlist
114P114I/OSynthesized pin mapping for EDA symbol-footprint netlist
115P115I/OSynthesized pin mapping for EDA symbol-footprint netlist
116P116I/OSynthesized pin mapping for EDA symbol-footprint netlist
117P117I/OSynthesized pin mapping for EDA symbol-footprint netlist
118P118I/OSynthesized pin mapping for EDA symbol-footprint netlist
119P119I/OSynthesized pin mapping for EDA symbol-footprint netlist
120P120I/OSynthesized pin mapping for EDA symbol-footprint netlist
121P121I/OSynthesized pin mapping for EDA symbol-footprint netlist
122P122I/OSynthesized pin mapping for EDA symbol-footprint netlist
123P123I/OSynthesized pin mapping for EDA symbol-footprint netlist
124P124I/OSynthesized pin mapping for EDA symbol-footprint netlist
125P125I/OSynthesized pin mapping for EDA symbol-footprint netlist
126P126I/OSynthesized pin mapping for EDA symbol-footprint netlist
127P127I/OSynthesized pin mapping for EDA symbol-footprint netlist
128P128I/OSynthesized pin mapping for EDA symbol-footprint netlist
PIN 1 P1
I/O
Multiplexed I/O & Peripheral Pin P1 (General)
Design note: Signal terminal P1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9130L (WCH · LQFP-128(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9130L (LQFP-128(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9130L (LQFP-128(14x14)) - 2. Standard Pinout (Top View)
True package pinout (128 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9130L (LQFP-128(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9130L (LQFP-128(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-128(14x14) · 14.00×14.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9130L (LQFP-128(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (128 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9130L (LQFP-128(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (CH9130L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9130L (LQFP-128(14x14)) is a 32-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-128(14x14))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol128 auto-grouped pins
OK
IPC-7351B Land Pattern128 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-128(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
128P / 128Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-128(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9130L (LQFP-128(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9130L (LQFP-128(14x14))?

Manufactured by WCH, the CH9130L is housed in a LQFP-128(14x14) package with 128 pins and a 0.40 mm lead pitch. Key pins include: 1 (P1: Multiplexed I/O & Peripheral Pin P1 (General)), 2 (P2: Multiplexed I/O & Peripheral Pin P2 (General)), 3 (P3: Multiplexed I/O & Peripheral Pin P3 (General)), 4 (P4: Multiplexed I/O & Peripheral Pin P4 (General)), 5 (P5: Multiplexed I/O & Peripheral Pin P5 (General)), 6 (P6: Multiplexed I/O & Peripheral Pin P6 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9130L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9130L (LQFP-128(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.40 mm, and 128 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9130L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9130L (WCH, LQFP-128(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (128 pins) & CH9130 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P1Digital_IOSignal terminal P1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1. Supported peripheral buses: General.
2P2Digital_IOSignal terminal P2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2. Supported peripheral buses: General.
3P3Digital_IOSignal terminal P3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3. Supported peripheral buses: General.
4P4Digital_IOSignal terminal P4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4. Supported peripheral buses: General.
5P5Digital_IOSignal terminal P5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5. Supported peripheral buses: General.
6P6Digital_IOSignal terminal P6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6. Supported peripheral buses: General.
7P7Digital_IOSignal terminal P7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P7. Supported peripheral buses: General.
8P8Digital_IOSignal terminal P8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P8. Supported peripheral buses: General.
9P9Digital_IOSignal terminal P9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P9. Supported peripheral buses: General.
10P10Digital_IOSignal terminal P10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P10. Supported peripheral buses: General.
11P11Digital_IOSignal terminal P11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P11. Supported peripheral buses: General.
12P12Digital_IOSignal terminal P12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P12. Supported peripheral buses: General.
13P13Digital_IOSignal terminal P13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P13. Supported peripheral buses: General.
14P14Digital_IOSignal terminal P14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P14. Supported peripheral buses: General.
15P15Digital_IOSignal terminal P15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P15. Supported peripheral buses: General.
16P16Digital_IOSignal terminal P16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P16. Supported peripheral buses: General.
17P17Digital_IOSignal terminal P17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P17. Supported peripheral buses: General.
18P18Digital_IOSignal terminal P18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P18. Supported peripheral buses: General.
19P19Digital_IOSignal terminal P19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P19. Supported peripheral buses: General.
20P20Digital_IOSignal terminal P20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P20. Supported peripheral buses: General.
21P21Digital_IOSignal terminal P21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P21. Supported peripheral buses: General.
22P22Digital_IOSignal terminal P22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P22. Supported peripheral buses: General.
23P23Digital_IOSignal terminal P23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P23. Supported peripheral buses: General.
24P24Digital_IOSignal terminal P24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P24. Supported peripheral buses: General.
25P25Digital_IOSignal terminal P25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P25. Supported peripheral buses: General.
26P26Digital_IOSignal terminal P26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P26. Supported peripheral buses: General.
27P27Digital_IOSignal terminal P27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P27. Supported peripheral buses: General.
28P28Digital_IOSignal terminal P28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P28. Supported peripheral buses: General.
29P29Digital_IOSignal terminal P29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P29. Supported peripheral buses: General.
30P30Digital_IOSignal terminal P30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P30. Supported peripheral buses: General.
31P31Digital_IOSignal terminal P31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P31. Supported peripheral buses: General.
32P32Digital_IOSignal terminal P32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P32. Supported peripheral buses: General.
33P33Digital_IOP33 (CH9130L)
34P34Digital_IOP34 (CH9130L)
35P35Digital_IOP35 (CH9130L)
36P36Digital_IOP36 (CH9130L)
37P37Digital_IOP37 (CH9130L)
38P38Digital_IOP38 (CH9130L)
39P39Digital_IOP39 (CH9130L)
40P40Digital_IOP40 (CH9130L)
41P41Digital_IOP41 (CH9130L)
42P42Digital_IOP42 (CH9130L)
43P43Digital_IOP43 (CH9130L)
44P44Digital_IOP44 (CH9130L)
45P45Digital_IOP45 (CH9130L)
46P46Digital_IOP46 (CH9130L)
47P47Digital_IOP47 (CH9130L)
48P48Digital_IOP48 (CH9130L)
49P49Digital_IOP49 (CH9130L)
50P50Digital_IOP50 (CH9130L)
51P51Digital_IOP51 (CH9130L)
52P52Digital_IOP52 (CH9130L)
53P53Digital_IOP53 (CH9130L)
54P54Digital_IOP54 (CH9130L)
55P55Digital_IOP55 (CH9130L)
56P56Digital_IOP56 (CH9130L)
57P57Digital_IOP57 (CH9130L)
58P58Digital_IOP58 (CH9130L)
59P59Digital_IOP59 (CH9130L)
60P60Digital_IOP60 (CH9130L)
61P61Digital_IOP61 (CH9130L)
62P62Digital_IOP62 (CH9130L)
63P63Digital_IOP63 (CH9130L)
64P64Digital_IOP64 (CH9130L)
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