ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH568L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH568L

WCHID: C963142LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH568L (LQFP-48(7x7))1GND2VCC333VCC124SRXP5SRXM6VCC12A7STXM8STXP9VCC12A10RSATA11PA1512PA1413PA1314PA1215PA216PA117PA018V33IO119PB720PB621PB522PB423PB324PB248V33IO247PA1146PA1045PA944PA843PA742PA641PA540PA439PA338RST#37PB1036PB1135VCC1234GND33V33IO332UD-31UD+30RUSB29XI28XO27VCC3326PB025PB1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
2VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
3VCC12PowerPower Supply Input (VCC12 — 3.3V / 5.0V Standard Logic)
4SRXPI/OMultiplexed I/O & Peripheral Pin SRXP (General)
5SRXMI/OMultiplexed I/O & Peripheral Pin SRXM (General)
6VCC12APowerPower Supply Input (VCC12A — 3.3V / 5.0V Standard Logic)
7STXMI/OMultiplexed I/O & Peripheral Pin STXM (General)
8STXPI/OMultiplexed I/O & Peripheral Pin STXP (General)
9VCC12APowerPower Supply Input (VCC12A — 3.3V / 5.0V Standard Logic)
10RSATAI/OMultiplexed I/O & Peripheral Pin RSATA (General)
11PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
12PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
13PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
14PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
15PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
16PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
17PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
18V33IO1PowerPower Supply Input (V33IO1 — 3.3V / 5.0V Standard Logic)
19PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
20PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
21PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
22PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
23PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
24PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
25PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
27VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
28XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
29XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
30RUSBI/OMultiplexed I/O & Peripheral Pin RUSB (General)
31UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
32UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
33V33IO3PowerPower Supply Input (V33IO3 — 3.3V / 5.0V Standard Logic)
34GNDGNDGround Reference Pin (GND)
35VCC12PowerPower Supply Input (VCC12 — 3.3V / 5.0V Standard Logic)
36PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
37PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
38RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
39PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
40PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
41PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
42PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
43PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
44PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
45PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
46PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
47PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
48V33IO2PowerPower Supply Input (V33IO2 — 3.3V / 5.0V Standard Logic)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH568L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH568L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH568L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH568L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH568L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH568L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH568L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH568
P2 · p02_fig01EXACT PACKAGE
CH568L (LQFP-48(7x7)) — Figure 2-1 Pin arrangement of LQFP48 package 1.2 Pin Description
Figure 2-1 Pin arrangement of LQFP48 package 1.2 Pin Description
P2 · p02_fig02EXACT PACKAGE
CH568L (LQFP-48(7x7)) — Figure 2-1 Pin arrangement of LQFP48 package 1.2 Pin Description
Figure 2-1 Pin arrangement of LQFP48 package 1.2 Pin Description
P1 · p01_fig01286×190px
CH568L (LQFP-48(7x7)) — Overview
Overview
P2 · p02_fig01P2
CH568L (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P2 · p02_fig02P2
CH568L (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig02)
Datasheet Page 2 (p02_fig02)
P6 · p06_fig011780×1085px
CH568L (LQFP-48(7x7)) — CH568 Datasheet 5 http://wch.cn
CH568 Datasheet 5 http://wch.cn
P10 · p10_fig011283×502px
CH568L (LQFP-48(7x7)) — Figure 3-1 Power-on Reset
Figure 3-1 Power-on Reset
P102 · p102_fig011611×1314px
CH568L (LQFP-48(7x7)) — Remarks: The unit of dimension is mm (millimeters) The pin center spacing is the nominal value, there is no error, and other dimension error is not greater than ±0.2mm.
Remarks: The unit of dimension is mm (millimeters) The pin center spacing is the nominal value, there is no error, and other dimension error is not greater than ±0.2mm.

Technical Specifications & Part Details (CH568L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH568L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, PWM, SDIO, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
120MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, PWM, SDIO, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH568L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH568L (LQFP-48(7x7))?

Manufactured by WCH, the CH568L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (VCC33: Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)), 3 (VCC12: Power Supply Input (VCC12 — 3.3V / 5.0V Standard Logic)), 4 (SRXP: Multiplexed I/O & Peripheral Pin SRXP (General)), 5 (SRXM: Multiplexed I/O & Peripheral Pin SRXM (General)), 6 (VCC12A: Power Supply Input (VCC12A — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH568L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH568L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH568L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH568L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH568 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
2VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3VCC12Power_InPrimary positive power supply input (VCC12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4SRXPDigital_IOSignal terminal SRXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SRXP. Supported peripheral buses: General.
5SRXMDigital_IOSignal terminal SRXM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SRXM. Supported peripheral buses: General.
6VCC12APower_InPrimary positive power supply input (VCC12A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7STXMDigital_IOSignal terminal STXM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STXM. Supported peripheral buses: General.
8STXPDigital_IOSignal terminal STXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STXP. Supported peripheral buses: General.
9VCC12APower_InPrimary positive power supply input (VCC12A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10RSATADigital_IOSignal terminal RSATA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSATA. Supported peripheral buses: General.
11PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
12PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
13PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
14PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
15PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
16PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
17PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
18V33IO1Power_InPrimary positive power supply input (V33IO1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
20PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
21PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
22PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
23PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
24PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
25PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
27VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
29XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
30RUSBDigital_IOSignal terminal RUSB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RUSB. Supported peripheral buses: General.
31UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
32UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
33V33IO3Power_InPrimary positive power supply input (V33IO3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
35VCC12Power_InPrimary positive power supply input (VCC12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
37PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
38RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
39PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
40PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
41PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
42PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
43PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
44PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
45PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
46PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
47PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
48V33IO2Power_InPrimary positive power supply input (V33IO2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
ExplorePartsPackagesMFRsUpload