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CH412K (SOT-363-6) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH412K

WCHID: C89184SOT-363-6 · 6 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH412K (SOT-363-6)1IO12GND3IO26IO1～IO45VCC4IO3Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.210.25.10-5.1-10.2mm
2. 2D FOOTPRINT
123456E=2.00mm · Pitch e=0.65mmD=1.25mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 1.25mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (6/6)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OMultiplexed I/O & Peripheral Pin IO1 (General)
2GNDGNDGround Reference Pin (GND)
3IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
4IO3I/OMultiplexed I/O & Peripheral Pin IO3 (General)
5VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
6IO1～IO4I/OMultiplexed I/O & Peripheral Pin IO1～IO4 (General)
PIN 1 IO1
I/O
Multiplexed I/O & Peripheral Pin IO1 (General)
Design note: Signal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH412K (WCH · SOT-363-6)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH412K (SOT-363-6) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH412K (SOT-363-6) - 2. Standard Pinout (Top View)
True package pinout (6 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH412K (SOT-363-6) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH412K (SOT-363-6) - 4. Package Dimensions (D×E×A)
SOT-363-6 · 2.00×1.25mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH412K (SOT-363-6) - 5. Recommended Land Pattern
IPC-7351B Footprint (6 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH412K (SOT-363-6) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH412
P1 · p01_fig011756×604px
CH412K (SOT-363-6) — 2、特点
2、特点
P1 · p01_fig02805×204px
CH412K (SOT-363-6) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOT363 1.25mm 49mil 0.65mm 26mil 小型6 脚贴片 CH412K SOT353 1.25mm 49mil 0.65mm 26mil 小型5 脚贴片 CH412Z 注：1、封装体积较小，正面印字仅有代号而不含全部型号，例如CH412Z 代号是12。 2、盘装，每盘整包装数量为3000 只，可以零售，但是零售时不会逐个清点数量。 CH412K CH4122 4 Idi 104 é 4 loi rlo4
封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOT363 1.25mm 49mil 0.65mm 26mil 小型6 脚贴片 CH412K SOT353 1.25mm 49mil 0.65mm 26mil 小型5 脚贴片 CH412Z 注：1、封装体积较小，正面印字仅有代号而不含全部型号，例如CH412Z 代号是12。 2、盘装，每盘整包装数量为3000 只，可以零售，但是零售时不会逐个清点数量。 CH412K CH4122 4 Idi 104 é 4 loi rlo4
P1 · p01_fig02P1
CH412K (SOT-363-6) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P2 · p02_fig011726×745px
CH412K (SOT-363-6) — 6.1. 绝对最大值（临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏）
6.1. 绝对最大值（临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏）
P3 · p03_fig011500×532px
CH412K (SOT-363-6) — CH412K 可以用于USB 高速信号的ESD 保护，GND 直接连接到全局地，VCC 连接到3.3V 电源电压， 并且由电容C4 提供电源旁路。
CH412K 可以用于USB 高速信号的ESD 保护，GND 直接连接到全局地，VCC 连接到3.3V 电源电压， 并且由电容C4 提供电源旁路。
P3 · p03_fig021290×727px
CH412K (SOT-363-6) — 7.2. CH412Z 应用（下图）
7.2. CH412Z 应用（下图）
P3 · p03_fig01P3
CH412K (SOT-363-6) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011296×1486px
CH412K (SOT-363-6) — D i] =a] 7 qf i a EE.
D i] =a] 7 qf i a EE.
P4 · p04_fig01P4
CH412K (SOT-363-6) — Datasheet Page 4 (p04_fig01)
Datasheet Page 4 (p04_fig01)

Technical Specifications & Part Details (CH412K)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH412K (SOT-363-6) is a 6-pin standard electronic & interconnect component featuring a 2.00 × 1.25 × 0.95 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 1.25 × 0.95 mm (A1=0.10 mm)
Package family: SOT23 (SOT-363-6)
Pin Count & Lead PitchN / e
6 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol6 auto-grouped pins
OK
IPC-7351B Land Pattern6 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOT-363-6)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.00 × 1.25 mm
Height (A) & Pitch (e)IPC-7351B
A=0.95mm · e=0.65mm
Pad Size (W × L)Level B
0.30 × 1.07 mm
Pins / Total PadsTopology
6P / 6Pad (SOT_SMALL)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOT-363-6
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH412K (SOT-363-6)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH412K (SOT-363-6)?

Manufactured by WCH, the CH412K is housed in a SOT-363-6 package with 6 pins and a 0.65 mm lead pitch. Key pins include: 1 (IO1: Multiplexed I/O & Peripheral Pin IO1 (General)), 2 (GND: Ground Reference Pin (GND)), 3 (IO2: Multiplexed I/O & Peripheral Pin IO2 (General)), 4 (IO3: Multiplexed I/O & Peripheral Pin IO3 (General)), 5 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 6 (IO1～IO4: Multiplexed I/O & Peripheral Pin IO1～IO4 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH412K?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH412K (SOT-363-6) has a nominal body envelope of 1.25 × 2.00 mm, pitch e = 0.65 mm, and 6 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH412K?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH412K (WCH, SOT-363-6) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (6 pins) & CH412 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOSignal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
4IO3Digital_IOSignal terminal IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3. Supported peripheral buses: General.
5VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6IO1～IO4Digital_IOSignal terminal IO1～IO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1～IO4. Supported peripheral buses: General.
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