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CH559T (SSOP-20-208mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH559T

WCHID: C85215SSOP-20-208mil · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH559T (SSOP-20-208mil)1P1.2/AIN2/PW2P1.4/AIN4/SC3P1.5/AIN5/MO4P1.6/AIN6/MI5P1.7/AIN7SCK6P5.7/RST7P3.2/LED0/IN8P3.4/LEDC/T09P4.6/XI/SCS_10P4.7/XO/SCK_20VDD3319VIN518GND17P02 .16P03 .15P5.0/DM14P5.1/DP13P2.7/TXD112P2.6/RXD111IO6Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=5.30mm · Pitch e=0.65mmD=7.20mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 5.30mm × 7.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P1.2/AIN2/PWM3/CAP3I/OMultiplexed I/O & Peripheral Pin P1.2/AIN2/PWM3/CAP3 (ADC, PWM)
2P1.4/AIN4/SCSI/OMultiplexed I/O & Peripheral Pin P1.4/AIN4/SCS (ADC)
3P1.5/AIN5/MOSII/OMultiplexed I/O & Peripheral Pin P1.5/AIN5/MOSI (SPI, ADC)
4P1.6/AIN6/MISOI/OMultiplexed I/O & Peripheral Pin P1.6/AIN6/MISO (SPI, ADC)
5P1.7/AIN7SCKI/OMultiplexed I/O & Peripheral Pin P1.7/AIN7SCK (ADC)
6P5.7/RSTI/OMultiplexed I/O & Peripheral Pin P5.7/RST (General)
7P3.2/LED0/INT0I/OMultiplexed I/O & Peripheral Pin P3.2/LED0/INT0 (General)
8P3.4/LEDC/T0I/OMultiplexed I/O & Peripheral Pin P3.4/LEDC/T0 (General)
9P4.6/XI/SCS_I/OMultiplexed I/O & Peripheral Pin P4.6/XI/SCS_ (RTC/CLK)
10P4.7/XO/SCK_I/OMultiplexed I/O & Peripheral Pin P4.7/XO/SCK_ (SPI, RTC/CLK)
11IO6I/OGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12P2.6/RXD1I/OMultiplexed I/O & Peripheral Pin P2.6/RXD1 (UART)
13P2.7/TXD1I/OMultiplexed I/O & Peripheral Pin P2.7/TXD1 (UART)
14P5.1/DPI/OMultiplexed I/O & Peripheral Pin P5.1/DP (General)
15P5.0/DMI/OMultiplexed I/O & Peripheral Pin P5.0/DM (General)
16P03 .I/OMultiplexed I/O & Peripheral Pin P03 . (UART)
17P02 .I/OMultiplexed I/O & Peripheral Pin P02 . (UART)
18GNDGNDGround Reference Pin (GND)
19VIN5PowerPower Supply Input (VIN5 — 5V to 3.3V)
20VDD33PowerRegulated Power Output (VDD33 — 5V to 3.3V)
PIN 1 P1.2/AIN2/PWM3/CAP3
I/O
Multiplexed I/O & Peripheral Pin P1.2/AIN2/PWM3/CAP3 (ADC, PWM)
Design note: Signal terminal P1.2/AIN2/PWM3/CAP3 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.2/AIN2/PWM3/CAP3. Supported peripheral buses: ADC, PWM.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH559T (WCH · SSOP-20-208mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH559T (SSOP-20-208mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH559T (SSOP-20-208mil) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH559T (SSOP-20-208mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH559T (SSOP-20-208mil) - 4. Package Dimensions (D×E×A)
SSOP-20-208mil · 5.30×7.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH559T (SSOP-20-208mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH559T (SSOP-20-208mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH559
P1 · p01_fig011745×914px
CH559T (SSOP-20-208mil) — Here is CH559 internal block diagram, for reference only.
Here is CH559 internal block diagram, for reference only.
P3 · p03_fig011736×980px
CH559T (SSOP-20-208mil) — Package Body size Lead pitch Description Part No.
Package Body size Lead pitch Description Part No.
P3 · p03_fig01P3
CH559T (SSOP-20-208mil) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P91 · p91_fig011790×1236px
CH559T (SSOP-20-208mil) — CH559 Datasheet 91 http://wch.cn
CH559 Datasheet 91 http://wch.cn

Technical Specifications & Part Details (CH559T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH559T (SSOP-20-208mil) is a 20-pin standard electronic & interconnect component featuring a 7.20 × 5.30 × 2.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 5V to 3.3V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
5V to 3.3V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
56MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.20 × 5.30 × 2.00 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-20-208mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-20-208mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=2.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-20-208mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH559T (SSOP-20-208mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH559T (SSOP-20-208mil)?

Manufactured by WCH, the CH559T is housed in a SSOP-20-208mil package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 5V to 3.3V. Key pins include: 1 (P1.2/AIN2/PWM3/CAP3: Multiplexed I/O & Peripheral Pin P1.2/AIN2/PWM3/CAP3 (ADC, PWM)), 2 (P1.4/AIN4/SCS: Multiplexed I/O & Peripheral Pin P1.4/AIN4/SCS (ADC)), 3 (P1.5/AIN5/MOSI: Multiplexed I/O & Peripheral Pin P1.5/AIN5/MOSI (SPI, ADC)), 4 (P1.6/AIN6/MISO: Multiplexed I/O & Peripheral Pin P1.6/AIN6/MISO (SPI, ADC)), 5 (P1.7/AIN7SCK: Multiplexed I/O & Peripheral Pin P1.7/AIN7SCK (ADC)), 6 (P5.7/RST: Multiplexed I/O & Peripheral Pin P5.7/RST (General)).

What are the IPC-7351B PCB Footprint dimensions for CH559T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH559T (SSOP-20-208mil) has a nominal body envelope of 5.30 × 7.20 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH559T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH559T (WCH, SSOP-20-208mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH559 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P1.2/AIN2/PWM3/CAP3AnalogSignal terminal P1.2/AIN2/PWM3/CAP3 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.2/AIN2/PWM3/CAP3. Supported peripheral buses: ADC, PWM.
2P1.4/AIN4/SCSAnalogSignal terminal P1.4/AIN4/SCS (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.4/AIN4/SCS. Supported peripheral buses: ADC.
3P1.5/AIN5/MOSIDigital_IOSignal terminal P1.5/AIN5/MOSI (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.5/AIN5/MOSI. Supported peripheral buses: SPI, ADC.
4P1.6/AIN6/MISODigital_IOSignal terminal P1.6/AIN6/MISO (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.6/AIN6/MISO. Supported peripheral buses: SPI, ADC.
5P1.7/AIN7SCKDigital_IOSignal terminal P1.7/AIN7SCK (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.7/AIN7SCK. Supported peripheral buses: ADC.
6P5.7/RSTDigital_IOSignal terminal P5.7/RST (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.7/RST. Supported peripheral buses: General.
7P3.2/LED0/INT0Digital_IOSignal terminal P3.2/LED0/INT0 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.2/LED0/INT0. Supported peripheral buses: General.
8P3.4/LEDC/T0Digital_IOSignal terminal P3.4/LEDC/T0 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.4/LEDC/T0. Supported peripheral buses: General.
9P4.6/XI/SCS_Digital_IOSignal terminal P4.6/XI/SCS_ (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.6/XI/SCS_. Supported peripheral buses: RTC/CLK.
10P4.7/XO/SCK_Digital_IOSignal terminal P4.7/XO/SCK_ (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.7/XO/SCK_. Supported peripheral buses: SPI, RTC/CLK.
11IO6Digital_IOGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12P2.6/RXD1Digital_IOSignal terminal P2.6/RXD1 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.6/RXD1. Supported peripheral buses: UART.
13P2.7/TXD1Digital_IOSignal terminal P2.7/TXD1 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.7/TXD1. Supported peripheral buses: UART.
14P5.1/DPDigital_IOSignal terminal P5.1/DP (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.1/DP. Supported peripheral buses: General.
15P5.0/DMDigital_IOSignal terminal P5.0/DM (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.0/DM. Supported peripheral buses: General.
16P03 .Digital_IOSignal terminal P03 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P03 .. Supported peripheral buses: UART.
17P02 .Digital_IOSignal terminal P02 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P02 .. Supported peripheral buses: UART.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19VIN5Power_InPrimary positive power supply input (VIN5) operating in the 5V to 3.3V domain (Max rating: 5.0V).
20VDD33Power_OutRegulated power output rail (VDD33) operating in the 5V to 3.3V domain (Max rating: 5.0V).
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