ChipDocs.org
⌘K
2284 PARTSUpload PDF
MCP4461-502E/ST (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

MCP4461-502E/ST

MICROCHIPID: C638709TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MCP4461-502E/ST (TSSOP-20)1P3A2P3W3P3B4HVC/A05SCL6SDA7VSS8P1B9P1W10P1A20P2A19P2W18P2B17VDD16A115RESET#14WP#13P0B12P0W11P0AGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P3AI/OMultiplexed I/O & Peripheral Pin P3A (General)
2P3WI/OMultiplexed I/O & Peripheral Pin P3W (General)
3P3BI/OMultiplexed I/O & Peripheral Pin P3B (General)
4HVC/A0I/OMultiplexed I/O & Peripheral Pin HVC/A0 (General)
5SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
6SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
7VSSGNDGround Reference Pin (VSS)
8P1BI/OMultiplexed I/O & Peripheral Pin P1B (General)
9P1WI/OMultiplexed I/O & Peripheral Pin P1W (General)
10P1AI/OMultiplexed I/O & Peripheral Pin P1A (General)
11P0AI/OMultiplexed I/O & Peripheral Pin P0A (General)
12P0WI/OMultiplexed I/O & Peripheral Pin P0W (General)
13P0BI/OMultiplexed I/O & Peripheral Pin P0B (General)
14WP#I/OMultiplexed I/O & Peripheral Pin WP# (General)
15RESET#ISystem Enable & Hardware Reset (RESET#)
16A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
17VDDPowerPower Supply Input (VDD — 2.7V to 5.5V)
18P2BI/OMultiplexed I/O & Peripheral Pin P2B (General)
19P2WI/OMultiplexed I/O & Peripheral Pin P2W (General)
20P2AI/OMultiplexed I/O & Peripheral Pin P2A (General)
PIN 1 P3A
I/O
Multiplexed I/O & Peripheral Pin P3A (General)
Design note: Signal terminal P3A (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3A. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MCP4461-502E/ST (MICROCHIP · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MCP4461-502E/ST (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MCP4461-502E/ST (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MCP4461-502E/ST (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MCP4461-502E/ST (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
MCP4461-502E/ST (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
MCP4461-502E/ST (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for MCP4461
P1 · p01_fig01377×200px
MCP4461-502E/ST (TSSOP-20) — 7/8-Bit Quad I2C Digital POT with Nonvolatile Memory
7/8-Bit Quad I2C Digital POT with Nonvolatile Memory
P2 · p02_fig011766×2045px
MCP4461-502E/ST (TSSOP-20) — MCP4432 (3) 4 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V
MCP4432 (3) 4 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V
P2 · p02_fig021782×774px
MCP4461-502E/ST (TSSOP-20) — P3B
P3B
P74 · p74_fig011785×1144px
MCP4461-502E/ST (TSSOP-20) — FIGURE 8-3: Example Application Circuit using Terminal Disconnects.
FIGURE 8-3: Example Application Circuit using Terminal Disconnects.
P75 · p75_fig011781×1253px
MCP4461-502E/ST (TSSOP-20) — FIGURE 8-5: Typical Application I2C Bus Configurations.
FIGURE 8-5: Typical Application I2C Bus Configurations.
P78 · p78_fig011781×1272px
MCP4461-502E/ST (TSSOP-20) — FIGURE 8-9: Quad Pinout (TSSOP Package) vs. Dual Pinout.
FIGURE 8-9: Quad Pinout (TSSOP Package) vs. Dual Pinout.
P79 · p79_fig011779×979px
MCP4461-502E/ST (TSSOP-20) — Figure 8-10 shows possible layout implementations for an application to support the quad and dual options on the same PCB.
Figure 8-10 shows possible layout implementations for an application to support the quad and dual options on the same PCB.
P81 · p81_fig02455×1439px
MCP4461-502E/ST (TSSOP-20) — Example | 4462502E | 1035 | 256 | Example | 4461 502EML | 256 ^^3 e | Example | 1035 | 4461502 | EST 256 | 1035 ^^3 e
Example | 4462502E | 1035 | 256 | Example | 4461 502EML | 256 ^^3 e | Example | 1035 | 4461502 | EST 256 | 1035 ^^3 e
P81 · p81_fig031777×755px
MCP4461-502E/ST (TSSOP-20) — © 2010 Microchip Technology Inc. DS22265A-page 81 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spec
© 2010 Microchip Technology Inc. DS22265A-page 81 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spec
P81 · p81_fig03P81
MCP4461-502E/ST (TSSOP-20) — Datasheet Page 81 (p81_fig03)
Datasheet Page 81 (p81_fig03)
P95 · p95_fig011777×919px
MCP4461-502E/ST (TSSOP-20) — Variation
Variation
P95 · p95_fig01P95
MCP4461-502E/ST (TSSOP-20) — Datasheet Page 95 (p95_fig01)
Datasheet Page 95 (p95_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (MCP4461-502E/ST)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MCP4461-502E/ST (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.7V to 5.5V supply operation across 0°C to 70°C with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
0°C to 70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
100 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP4461-502E/ST (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP4461-502E/ST (TSSOP-20)?

Manufactured by MICROCHIP, the MCP4461-502E/ST is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (P3A: Multiplexed I/O & Peripheral Pin P3A (General)), 2 (P3W: Multiplexed I/O & Peripheral Pin P3W (General)), 3 (P3B: Multiplexed I/O & Peripheral Pin P3B (General)), 4 (HVC/A0: Multiplexed I/O & Peripheral Pin HVC/A0 (General)), 5 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 6 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)).

What are the IPC-7351B PCB Footprint dimensions for MCP4461-502E/ST?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP4461-502E/ST (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP4461-502E/ST?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP4461-502E/ST (MICROCHIP, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & MCP4461 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P3ADigital_IOSignal terminal P3A (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3A. Supported peripheral buses: General.
2P3WDigital_IOSignal terminal P3W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3W. Supported peripheral buses: General.
3P3BDigital_IOSignal terminal P3B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3B. Supported peripheral buses: General.
4HVC/A0Digital_IOSignal terminal HVC/A0 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: HVC/A0. Supported peripheral buses: General.
5SCLDigital_IOSignal terminal SCL (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
6SDADigital_IOSignal terminal SDA (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
8P1BDigital_IOSignal terminal P1B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1B. Supported peripheral buses: General.
9P1WDigital_IOSignal terminal P1W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1W. Supported peripheral buses: General.
10P1ADigital_IOSignal terminal P1A (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1A. Supported peripheral buses: General.
11P0ADigital_IOSignal terminal P0A (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0A. Supported peripheral buses: General.
12P0WDigital_IOSignal terminal P0W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0W. Supported peripheral buses: General.
13P0BDigital_IOSignal terminal P0B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0B. Supported peripheral buses: General.
14WP#Digital_IOSignal terminal WP# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: WP#. Supported peripheral buses: General.
15RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
16A1Digital_IOSignal terminal A1 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
18P2BDigital_IOSignal terminal P2B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2B. Supported peripheral buses: General.
19P2WDigital_IOSignal terminal P2W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2W. Supported peripheral buses: General.
20P2ADigital_IOSignal terminal P2A (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2A. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload