MCP73213-B6SI/MF (DFN-10(3x3)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of MCP73213-B6SI/MF (DFN-10(3x3))?

Manufactured by MICROCHIP, the MCP73213-B6SI/MF is housed in a DFN-10(3x3) package with 11 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 2 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 3 (VBAT: Regulated Power Output (VBAT — 3.3V / 5.0V Standard Logic)), 4 (VBAT: Regulated Power Output (VBAT — 3.3V / 5.0V Standard Logic)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for MCP73213-B6SI/MF?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP73213-B6SI/MF (DFN-10(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.40 × 1.65 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP73213-B6SI/MF?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP73213-B6SI/MF (MICROCHIP, DFN-10(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 3.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (11/11)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
2	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
3	VBAT	Power	Regulated Power Output (VBAT — 3.3V / 5.0V Standard Logic)
4	VBAT	Power	Regulated Power Output (VBAT — 3.3V / 5.0V Standard Logic)
5	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
6	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
7	STAT	I/O	Multiplexed I/O & Peripheral Pin STAT (General)
8	VSS	GND	Ground Reference Pin (VSS)
9	VSS	GND	Ground Reference Pin (VSS)
10	PROG	I/O	Multiplexed I/O & Peripheral Pin PROG (General)
11	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 VDD

Power

Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)

Design note: BatteryManagementInputSupplyPin

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

MCP73213-B6SI/MF (DFN-10(3x3)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

MCP73213-B6SI/MF (DFN-10(3x3)) - 2. Standard Pinout (Top View)

True package pinout (11 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

MCP73213-B6SI/MF (DFN-10(3x3)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

MCP73213-B6SI/MF (DFN-10(3x3)) - 4. Package Dimensions (D×E×A)

DFN-10(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

MCP73213-B6SI/MF (DFN-10(3x3)) - 5. Recommended Land Pattern

IPC-7351B Footprint (11 Pads)Expand ›

6. Application SchematicSCHEMATIC

MCP73213-B6SI/MF (DFN-10(3x3)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)

Showing 1–12 of 12 uncropped original figures for MCP73213

P1 · p01_fig01377×200px

Dual-Cell Li-Ion/Li-Polymer Battery Charge Management

P1 · p01_fig02866×621px

 2009-2018 Microchip Technology Inc. DS20002190D-page 1

P2 · p02_fig011775×786px

MCP73213

P2 · p02_fig01P2

Datasheet Page 2 (p02_fig01)

P21 · p21_fig011775×785px

FIGURE 6-1: Typical Application Circuit.

P21 · p21_fig02724×477px

FIGURE 6-2: Typical Charge Profile (875 mAh Li-Ion Battery).

P23 · p23_fig01667×580px

FIGURE 6-5: Typical Layout (Bottom).

P23 · p23_fig02664×587px

FIGURE 6-3: Typical Layout (Top).

P23 · p23_fig03662×580px

FIGURE 6-4: Typical Layout (Top Metal).

P23 · p23_fig02P23

Datasheet Page 23 (p23_fig02)

P25 · p25_fig011777×785px

MCP73213-B6SI/MF (DFN-10(3x3)) —  2009-2018 Microchip Technology Inc. DS20002190D-page 25 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custo

 2009-2018 Microchip Technology Inc. DS20002190D-page 25 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custo

P25 · p25_fig01P25

Datasheet Page 25 (p25_fig01)

Technical Specifications & Part Details (MCP73213-B6SI/MF)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:MCP73213-B6SI/MF (DFN-10(3x3)) is a 10-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 5°C to +55°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

5°C to +55°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1 kHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

3.00 × 3.00 × 0.85 mm (A1=0.03 mm)

Package family: DFN (DFN-10(3x3))

Pin Count & Lead PitchN / e

10 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol11 auto-grouped pins

IPC-7351B Land Pattern11 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 2.40×1.65mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (DFN-10(3x3))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

3.00 × 3.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 0.67 mm

Pins / Total PadsTopology

11P / 11Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit DFN-10(3x3)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP73213-B6SI/MF (DFN-10(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP73213-B6SI/MF (DFN-10(3x3))?

Manufactured by MICROCHIP, the MCP73213-B6SI/MF is housed in a DFN-10(3x3) package with 11 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 2 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 3 (VBAT: Regulated Power Output (VBAT — 3.3V / 5.0V Standard Logic)), 4 (VBAT: Regulated Power Output (VBAT — 3.3V / 5.0V Standard Logic)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for MCP73213-B6SI/MF?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP73213-B6SI/MF (DFN-10(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.40 × 1.65 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP73213-B6SI/MF?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP73213-B6SI/MF (MICROCHIP, DFN-10(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (11 pins) & MCP73213 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3	VBAT	Power_Out	Regulated power output rail (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4	VBAT	Power_Out	Regulated power output rail (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7	STAT	Digital_IO	Signal terminal STAT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STAT. Supported peripheral buses: General.
8	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
10	PROG	Digital_IO	Signal terminal PROG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PROG. Supported peripheral buses: General.
11	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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