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HV230B1-G (LLGA-26(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

HV230B1-G

MICROCHIPID: C633265LLGA-26(6x6) · 26 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · HV230B1-G (LLGA-26(6x6))1SW42DIN3CLK4LE5CL6DOUT7SW78SW79SW610SW611SW512SW513SW426SW425SW524SW523SW622SW621SW720SW719DOUT18CLR17LE#16CLK15DIN14VDDGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526E=6.00mm · Pitch e=0.65mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (26/26)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1SW4I/OMultiplexed I/O & Peripheral Pin SW4 (General)
2DINI/OMultiplexed I/O & Peripheral Pin DIN (General)
3CLKI/OMultiplexed I/O & Peripheral Pin CLK (General)
4LEI/OMultiplexed I/O & Peripheral Pin LE (General)
5CLI/OMultiplexed I/O & Peripheral Pin CL (General)
6DOUTI/OMultiplexed I/O & Peripheral Pin DOUT (General)
7SW7I/OMultiplexed I/O & Peripheral Pin SW7 (General)
8SW7I/OMultiplexed I/O & Peripheral Pin SW7 (General)
9SW6I/OMultiplexed I/O & Peripheral Pin SW6 (General)
10SW6I/OMultiplexed I/O & Peripheral Pin SW6 (General)
11SW5I/OMultiplexed I/O & Peripheral Pin SW5 (General)
12SW5I/OMultiplexed I/O & Peripheral Pin SW5 (General)
13SW4I/OMultiplexed I/O & Peripheral Pin SW4 (General)
14VDDPowerPower Supply Input (VDD — 4.5V to 13.2V)
15DINI/OMultiplexed I/O & Peripheral Pin DIN (General)
16CLKI/OMultiplexed I/O & Peripheral Pin CLK (General)
17LE#I/OMultiplexed I/O & Peripheral Pin LE# (General)
18CLRI/OMultiplexed I/O & Peripheral Pin CLR (General)
19DOUTI/OMultiplexed I/O & Peripheral Pin DOUT (General)
20SW7I/OMultiplexed I/O & Peripheral Pin SW7 (General)
21SW7I/OMultiplexed I/O & Peripheral Pin SW7 (General)
22SW6I/OMultiplexed I/O & Peripheral Pin SW6 (General)
23SW6I/OMultiplexed I/O & Peripheral Pin SW6 (General)
24SW5I/OMultiplexed I/O & Peripheral Pin SW5 (General)
25SW5I/OMultiplexed I/O & Peripheral Pin SW5 (General)
26SW4I/OMultiplexed I/O & Peripheral Pin SW4 (General)
PIN 1 SW4
I/O
Multiplexed I/O & Peripheral Pin SW4 (General)
Design note: GND
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: HV230B1-G (MICROCHIP · LLGA-26(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
HV230B1-G (LLGA-26(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
HV230B1-G (LLGA-26(6x6)) - 2. Standard Pinout (Top View)
True package pinout (26 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
HV230B1-G (LLGA-26(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
HV230B1-G (LLGA-26(6x6)) - 4. Package Dimensions (D×E×A)
LLGA-26(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
HV230B1-G (LLGA-26(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (26 Pads)Expand ›
6. Application SchematicSCHEMATIC
HV230B1-G (LLGA-26(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for HV230
P1 · p01_fig011660×1439px
HV230B1-G (LLGA-26(6x6)) — Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
P2 · p02_fig01504×264px
HV230B1-G (LLGA-26(6x6)) — * This package is not recommended for new designs - Use 26-Lead LLGA (G1) -G indicates the part is RoHS compliant (Green)
* This package is not recommended for new designs - Use 26-Lead LLGA (G1) -G indicates the part is RoHS compliant (Green)
P2 · p02_fig021884×2049px
HV230B1-G (LLGA-26(6x6)) — Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
P2 · p02_fig01P2
HV230B1-G (LLGA-26(6x6)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P2 · p02_fig02P2
HV230B1-G (LLGA-26(6x6)) — Datasheet Page 2 (p02_fig02)
Datasheet Page 2 (p02_fig02)
P5 · p05_fig011597×1062px
HV230B1-G (LLGA-26(6x6)) — Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
P8 · p08_fig011900×1268px
HV230B1-G (LLGA-26(6x6)) — Bottom View | Pin 1 | Pin 2 | A | A1 | Seating | Plane | D | E | Note 1 (Index Area D/2 x E/2) | 1 | 26 | Top View | Side View | L L | b b | 1 | Detail A Detail B | 0.10 x 45O | Detail B | d3 | e | d1 | d2 7 x e | 7 x e | L1 | Detail A | x2
Bottom View | Pin 1 | Pin 2 | A | A1 | Seating | Plane | D | E | Note 1 (Index Area D/2 x E/2) | 1 | 26 | Top View | Side View | L L | b b | 1 | Detail A Detail B | 0.10 x 45O | Detail B | d3 | e | d1 | d2 7 x e | 7 x e | L1 | Detail A | x2
P9 · p09_fig011886×1258px
HV230B1-G (LLGA-26(6x6)) — 26-Lead LLGA Package Outline (G1) 6.00x6.00mm body, 0.60mm height (max), 0.65mm pitch
26-Lead LLGA Package Outline (G1) 6.00x6.00mm body, 0.60mm height (max), 0.65mm pitch
P9 · p09_fig01P9
HV230B1-G (LLGA-26(6x6)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P10 · p10_fig011791×1281px
HV230B1-G (LLGA-26(6x6)) — 26-Ball fpBGA Package Outline (GA) 6.00x5.35mm body, 1.20mm height (max), 0.65mm pitch
26-Ball fpBGA Package Outline (GA) 6.00x5.35mm body, 1.20mm height (max), 0.65mm pitch

Technical Specifications & Part Details (HV230B1-G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:HV230B1-G (LLGA-26(6x6)) is a 26-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.15 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 4.5V to 13.2V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
4.5V to 13.2V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
50MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.15 mm (A1=0.03 mm)
Package family: LGA (LLGA-26(6x6))
Pin Count & Lead PitchN / e
26 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol26 auto-grouped pins
OK
IPC-7351B Land Pattern26 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LLGA-26(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=0.65mm
Pad Size (W × L)Level B
0.40 × 0.40 mm
Pins / Total PadsTopology
26P / 26Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LLGA-26(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HV230B1-G (LLGA-26(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HV230B1-G (LLGA-26(6x6))?

Manufactured by MICROCHIP, the HV230B1-G is housed in a LLGA-26(6x6) package with 26 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 4.5V to 13.2V. Key pins include: 1 (SW4: Multiplexed I/O & Peripheral Pin SW4 (General)), 2 (DIN: Multiplexed I/O & Peripheral Pin DIN (General)), 3 (CLK: Multiplexed I/O & Peripheral Pin CLK (General)), 4 (LE: Multiplexed I/O & Peripheral Pin LE (General)), 5 (CL: Multiplexed I/O & Peripheral Pin CL (General)), 6 (DOUT: Multiplexed I/O & Peripheral Pin DOUT (General)).

What are the IPC-7351B PCB Footprint dimensions for HV230B1-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV230B1-G (LLGA-26(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 26 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV230B1-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV230B1-G (MICROCHIP, LLGA-26(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (26 pins) & HV230 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1SW4Digital_IOSignal terminal SW4 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW4. Supported peripheral buses: General.
2DINDigital_IOSignal terminal DIN (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: DIN. Supported peripheral buses: General.
3CLKDigital_IOSignal terminal CLK (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
4LEDigital_IOSignal terminal LE (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: LE. Supported peripheral buses: General.
5CLDigital_IOSignal terminal CL (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: CL. Supported peripheral buses: General.
6DOUTDigital_IOSignal terminal DOUT (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: DOUT. Supported peripheral buses: General.
7SW7Digital_IOSignal terminal SW7 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW7. Supported peripheral buses: General.
8SW7Digital_IOSignal terminal SW7 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW7. Supported peripheral buses: General.
9SW6Digital_IOSignal terminal SW6 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW6. Supported peripheral buses: General.
10SW6Digital_IOSignal terminal SW6 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW6. Supported peripheral buses: General.
11SW5Digital_IOSignal terminal SW5 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW5. Supported peripheral buses: General.
12SW5Digital_IOSignal terminal SW5 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW5. Supported peripheral buses: General.
13SW4Digital_IOSignal terminal SW4 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW4. Supported peripheral buses: General.
14VDDPower_InPrimary positive power supply input (VDD) operating in the 4.5V to 13.2V domain (Max rating: 13.2V).
15DINDigital_IOSignal terminal DIN (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: DIN. Supported peripheral buses: General.
16CLKDigital_IOSignal terminal CLK (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
17LE#Digital_IOSignal terminal LE# (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: LE#. Supported peripheral buses: General.
18CLRDigital_IOSignal terminal CLR (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: CLR. Supported peripheral buses: General.
19DOUTDigital_IOSignal terminal DOUT (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: DOUT. Supported peripheral buses: General.
20SW7Digital_IOSignal terminal SW7 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW7. Supported peripheral buses: General.
21SW7Digital_IOSignal terminal SW7 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW7. Supported peripheral buses: General.
22SW6Digital_IOSignal terminal SW6 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW6. Supported peripheral buses: General.
23SW6Digital_IOSignal terminal SW6 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW6. Supported peripheral buses: General.
24SW5Digital_IOSignal terminal SW5 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW5. Supported peripheral buses: General.
25SW5Digital_IOSignal terminal SW5 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW5. Supported peripheral buses: General.
26SW4Digital_IOSignal terminal SW4 (I/O, 4.5V to 13.2V domain). Multiplexed alternate functions: SW4. Supported peripheral buses: General.
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