Mechanical Dimensions & Land Pattern (MSOP-10)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit MSOP-10 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — TC1303C-ZS0EUNTR (MSOP-10)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of TC1303C-ZS0EUNTR (MSOP-10)?
Manufactured by MICROCHIP, the TC1303C-ZS0EUNTR is housed in a MSOP-10 package with 10 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 8V to 4.5V. Key pins include: 1 (—: Multiplexed I/O & Peripheral Pin — (General)), 2 (V IN2: Multiplexed I/O & Peripheral Pin V IN2 (General)), 3 (V OUT2: Multiplexed I/O & Peripheral Pin V OUT2 (General)), 4 (PG: Multiplexed I/O & Peripheral Pin PG (General)), 5 (A GND: Ground Reference Pin (A GND)), 6 (V /V FB OUT1: Multiplexed I/O & Peripheral Pin V /V FB OUT1 (General)).
What are the IPC-7351B PCB Footprint dimensions for TC1303C-ZS0EUNTR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TC1303C-ZS0EUNTR (MSOP-10) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 10 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TC1303C-ZS0EUNTR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TC1303C-ZS0EUNTR (MICROCHIP, MSOP-10) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (10 pins) & TC1304 / TC1303 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | — | Digital_IO | Signal terminal — (I/O, 8V to 4.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General. |
| 2 | V IN2 | Digital_IO | Signal terminal V IN2 (I/O, 8V to 4.5V domain). Multiplexed alternate functions: V IN2. Supported peripheral buses: General. |
| 3 | V OUT2 | Digital_IO | Signal terminal V OUT2 (I/O, 8V to 4.5V domain). Multiplexed alternate functions: V OUT2. Supported peripheral buses: General. |
| 4 | PG | Digital_IO | Signal terminal PG (I/O, 8V to 4.5V domain). Multiplexed alternate functions: PG. Supported peripheral buses: General. |
| 5 | A GND | GND | 0V electrical ground return terminal (A GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 6 | V /V FB OUT1 | Digital_IO | Signal terminal V /V FB OUT1 (I/O, 8V to 4.5V domain). Multiplexed alternate functions: V /V FB OUT1. Supported peripheral buses: General. |
| 7 | — | Digital_IO | Signal terminal — (I/O, 8V to 4.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General. |
| 8 | V IN1 | Digital_IO | Signal terminal V IN1 (I/O, 8V to 4.5V domain). Multiplexed alternate functions: V IN1. Supported peripheral buses: General. |
| 9 | L X | Digital_IO | Signal terminal L X (I/O, 8V to 4.5V domain). Multiplexed alternate functions: L X. Supported peripheral buses: General. |
| 10 | P GND | GND | 0V electrical ground return terminal (P GND) for internal core logic, I/O drivers, and analog sub-blocks. |