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ATSAMS70N19B-CN (LFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATSAMS70N19B-CN

MICROCHIPID: C612463LFBGA-100 · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATSAMS70N19B-CN (LFBGA-100)A1PB9A2PB8A3VBGA4HSDMA5PD4A6PD7A7PA31A8GNDUTMIA9PA28A10JTAGSELB1PD31B2PB13B3VDDUTMICB4HSDPB5PD3B6PD6B7PD8B8PD9B9PB4B10PD15C1PD0C2VDDINC3VDDOUTC4GNDPLLUSBC5VDDIOC6VDDCOREC7PA30C8PB5C9PD10C10PA1D1VREFPD2PD1D3VREFND4GNDANAD5PD5D6VDDCORED7VDDPLLD8PA0D9PD11D10PA2E1PB0E2PB1E3PD2E4GNDPLLE5VDDUTMIIE6VDDPLLU SBE7GNDE8PD13E9PB7E10PD12K10PA12K9PA10K8PA26K7PA24K6PD18K5PA23K4PD19K3PD20K2PA8K1PD30J10PD17J9PA9J8PA11J7PD28J6PA15J5PA16J4PD22J3PA22J2PA7J1PA21H10PA4H9PA5H8PA27H7PA25H6PA14H5PD21H4PD27H3PD25H2PB3H1PB2G10NRSTG9PD16G8PB6G7VDDIOG6VDDCOREG5PA13G4PD24G3PD26G2PA18G1PA17F10PD14F9PA3F8PB12F7TSTF6GNDF5GNDF4GNDF3VDDIOF2PA20F1PA19Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10B1B2B3B4B5B6B7B8B9B10C1C2C3C4C5C6C7C8C9C10D1D2D3D4D5D6D7D8D9D10E1E2E3E4E5E6E7E8E9E10F1F2F3F4F5F6F7F8F9F10G1G2G3G4G5G6G7G8G9G10H1H2H3H4H5H6H7H8H9H10J1J2J3J4J5J6J7J8J9J10K1K2K3K4K5K6K7K8K9K10E=9.00mm · Pitch e=0.80mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A2PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
A3VBGI/OMultiplexed I/O & Peripheral Pin VBG (General)
A4HSDMI/OMultiplexed I/O & Peripheral Pin HSDM (General)
A5PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
A6PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A7PA31I/OMultiplexed I/O & Peripheral Pin PA31 (General)
A8GNDUTMIGNDGround Reference Pin (GNDUTMI)
A9PA28I/OMultiplexed I/O & Peripheral Pin PA28 (General)
A10JTAGSELI/OMultiplexed I/O & Peripheral Pin JTAGSEL (SWD/JTAG)
B1PD31I/OMultiplexed I/O & Peripheral Pin PD31 (General)
B2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
B3VDDUTMICPowerPower Supply Input (VDDUTMIC — 3.0V to 3.6V)
B4HSDPI/OMultiplexed I/O & Peripheral Pin HSDP (General)
B5PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
B6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
B7PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
B8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
B9PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B10PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
C1PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
C2VDDINPowerPower Supply Input (VDDIN — 3.0V to 3.6V)
C3VDDOUTPowerPower Supply Input (VDDOUT — 3.0V to 3.6V)
C4GNDPLLUSBGNDGround Reference Pin (GNDPLLUSB)
C5VDDIOPowerPower Supply Input (VDDIO — 3.0V to 3.6V)
C6VDDCOREPowerPower Supply Input (VDDCORE — 3.0V to 3.6V)
C7PA30I/OMultiplexed I/O & Peripheral Pin PA30 (General)
C8PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
C9PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
C10PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
D1VREFPAnalogMultiplexed I/O & Peripheral Pin VREFP (General)
D2PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D3VREFNAnalogMultiplexed I/O & Peripheral Pin VREFN (General)
D4GNDANAGNDGround Reference Pin (GNDANA)
D5PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
D6VDDCOREPowerPower Supply Input (VDDCORE — 3.0V to 3.6V)
D7VDDPLLPowerPower Supply Input (VDDPLL — 3.0V to 3.6V)
D8PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
D9PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
D10PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
E1PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
E2PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
E3PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
E4GNDPLLGNDGround Reference Pin (GNDPLL)
E5VDDUTMIIPowerPower Supply Input (VDDUTMII — 3.0V to 3.6V)
E6VDDPLLU SBPowerPower Supply Input (VDDPLLU SB — 3.0V to 3.6V)
E7GNDGNDGround Reference Pin (GND)
E8PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
E9PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
E10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
F1PA19I/OMultiplexed I/O & Peripheral Pin PA19 (General)
F2PA20I/OMultiplexed I/O & Peripheral Pin PA20 (General)
F3VDDIOPowerPower Supply Input (VDDIO — 3.0V to 3.6V)
F4GNDGNDGround Reference Pin (GND)
F5GNDGNDGround Reference Pin (GND)
F6GNDGNDGround Reference Pin (GND)
F7TSTI/OMultiplexed I/O & Peripheral Pin TST (General)
F8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
F9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
F10PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
G1PA17I/OMultiplexed I/O & Peripheral Pin PA17 (General)
G2PA18I/OMultiplexed I/O & Peripheral Pin PA18 (General)
G3PD26I/OMultiplexed I/O & Peripheral Pin PD26 (General)
G4PD24I/OMultiplexed I/O & Peripheral Pin PD24 (General)
G5PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
G6VDDCOREPowerPower Supply Input (VDDCORE — 3.0V to 3.6V)
G7VDDIOPowerPower Supply Input (VDDIO — 3.0V to 3.6V)
G8PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
G9PD16I/OMultiplexed I/O & Peripheral Pin PD16 (General)
G10NRSTISystem Enable & Hardware Reset (NRST)
H1PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
H2PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
H3PD25I/OMultiplexed I/O & Peripheral Pin PD25 (General)
H4PD27I/OMultiplexed I/O & Peripheral Pin PD27 (General)
H5PD21I/OMultiplexed I/O & Peripheral Pin PD21 (General)
H6PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
H7PA25I/OMultiplexed I/O & Peripheral Pin PA25 (General)
H8PA27I/OMultiplexed I/O & Peripheral Pin PA27 (General)
H9PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
H10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
J1PA21I/OMultiplexed I/O & Peripheral Pin PA21 (General)
J2PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
J3PA22I/OMultiplexed I/O & Peripheral Pin PA22 (General)
J4PD22I/OMultiplexed I/O & Peripheral Pin PD22 (General)
J5PA16I/OMultiplexed I/O & Peripheral Pin PA16 (General)
J6PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
J7PD28I/OMultiplexed I/O & Peripheral Pin PD28 (General)
J8PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
J9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
J10PD17I/OMultiplexed I/O & Peripheral Pin PD17 (General)
K1PD30I/OMultiplexed I/O & Peripheral Pin PD30 (General)
K2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
K3PD20I/OMultiplexed I/O & Peripheral Pin PD20 (General)
K4PD19I/OMultiplexed I/O & Peripheral Pin PD19 (General)
K5PA23I/OMultiplexed I/O & Peripheral Pin PA23 (General)
K6PD18I/OMultiplexed I/O & Peripheral Pin PD18 (General)
K7PA24I/OMultiplexed I/O & Peripheral Pin PA24 (General)
K8PA26I/OMultiplexed I/O & Peripheral Pin PA26 (General)
K9PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
K10PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
PIN A1 PB9
I/O
Multiplexed I/O & Peripheral Pin PB9 (General)
Design note: Signal terminal PB9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATSAMS70N19B-CN (MICROCHIP · LFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATSAMS70N19B-CN (LFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATSAMS70N19B-CN (LFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATSAMS70N19B-CN (LFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATSAMS70N19B-CN (LFBGA-100) - 4. Package Dimensions (D×E×A)
LFBGA-100 · 9.00×9.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATSAMS70N19B-CN (LFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATSAMS70N19B-CN (LFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for ATSAMS70N19B
P35 · p35_fig01EXACT PACKAGE
ATSAMS70N19B-CN (LFBGA-100) — Figure 6-4. Orientation of the 100-lead LQFP Package
Figure 6-4. Orientation of the 100-lead LQFP Package
P35 · p35_fig02EXACT PACKAGE
ATSAMS70N19B-CN (LFBGA-100) — Figure 6-5. Orientation of the 100-ball TFBGA Package
Figure 6-5. Orientation of the 100-ball TFBGA Package
P1924 · p1924_fig01EXACT PACKAGE
ATSAMS70N19B-CN (LFBGA-100) — Complete Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries
Complete Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries
P1926 · p1926_fig01EXACT PACKAGE
ATSAMS70N19B-CN (LFBGA-100) — SAM E70/S70/V70/V71 | Packaging Information | Complete Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries | DS60001527H - 1926 | 61.7 VFBGA100, 100-ball VFBGA | VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm | Table 61-13. De
SAM E70/S70/V70/V71 | Packaging Information | Complete Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries | DS60001527H - 1926 | 61.7 VFBGA100, 100-ball VFBGA | VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm | Table 61-13. De
P1952 · p1952_fig01EXACT PACKAGE
ATSAMS70N19B-CN (LFBGA-100) — SAM E70/S70/V70/V71 | Revision History | ...........continued | Date Changes | Section 5. “Package and Pinout” In all pinout tables, modified signal names to VREFP and VREFN (were ADVREFP and ADVREFN). | Replaced tables “Pinout for 100-pin
SAM E70/S70/V70/V71 | Revision History | ...........continued | Date Changes | Section 5. “Package and Pinout” In all pinout tables, modified signal names to VREFP and VREFN (were ADVREFP and ADVREFN). | Replaced tables “Pinout for 100-pin
P1180 · p1180_fig01847×502px
ATSAMS70N19B-CN (LFBGA-100) — Figure 45-35. Typical Connection to a RS485 Bus
Figure 45-35. Typical Connection to a RS485 Bus
P1180 · p1180_fig021105×639px
ATSAMS70N19B-CN (LFBGA-100) — Figure 45-36. Example of RTS Drive with Timeguard
Figure 45-36. Example of RTS Drive with Timeguard
P1180 · p1180_fig01P1180
ATSAMS70N19B-CN (LFBGA-100) — Datasheet Page 1180 (p1180_fig01)
Datasheet Page 1180 (p1180_fig01)
P1813 · p1813_fig011929×2188px
ATSAMS70N19B-CN (LFBGA-100) — SAM E70/S70/V70/V71 Electrical Characteristics for SAM V70/V71
SAM E70/S70/V70/V71 Electrical Characteristics for SAM V70/V71
P1855 · p1855_fig011929×2188px
ATSAMS70N19B-CN (LFBGA-100) — SAM E70/S70/V70/V71 Electrical Characteristics for SAM E70/S70
SAM E70/S70/V70/V71 Electrical Characteristics for SAM E70/S70
P1898 · p1898_fig011775×1515px
ATSAMS70N19B-CN (LFBGA-100) — Complete Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries
Complete Data Sheet © 2023 Microchip Technology Inc. and its subsidiaries
P1898 · p1898_fig01P1898
ATSAMS70N19B-CN (LFBGA-100) — Datasheet Page 1898 (p1898_fig01)
Datasheet Page 1898 (p1898_fig01)
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (ATSAMS70N19B-CN)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATSAMS70N19B-CN (LFBGA-100) is a 100-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 1.10 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V to 3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, DAC, PWM, SDIO, IrDA, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
300 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 1.10 mm (A1=0.30 mm)
Package family: BGA (LFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, DAC, PWM, SDIO, IrDA, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=0.80mm
Pad Size (W × L)Level B
0.40 × 0.40 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATSAMS70N19B-CN (LFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATSAMS70N19B-CN (LFBGA-100)?

Manufactured by MICROCHIP, the ATSAMS70N19B-CN is housed in a LFBGA-100 package with 100 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: A1 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A2 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), A3 (VBG: Multiplexed I/O & Peripheral Pin VBG (General)), A4 (HSDM: Multiplexed I/O & Peripheral Pin HSDM (General)), A5 (PD4: Multiplexed I/O & Peripheral Pin PD4 (General)), A6 (PD7: Multiplexed I/O & Peripheral Pin PD7 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATSAMS70N19B-CN?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATSAMS70N19B-CN (LFBGA-100) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATSAMS70N19B-CN?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATSAMS70N19B-CN (MICROCHIP, LFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & ATSAMS70N19B Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PB9Digital_IOSignal terminal PB9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A2PB8Digital_IOSignal terminal PB8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
A3VBGDigital_IOSignal terminal VBG (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VBG. Supported peripheral buses: General.
A4HSDMDigital_IOSignal terminal HSDM (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: HSDM. Supported peripheral buses: General.
A5PD4Digital_IOSignal terminal PD4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
A6PD7Digital_IOSignal terminal PD7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A7PA31Digital_IOSignal terminal PA31 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA31. Supported peripheral buses: General.
A8GNDUTMIGND0V electrical ground return terminal (GNDUTMI) for internal core logic, I/O drivers, and analog sub-blocks.
A9PA28Digital_IOSignal terminal PA28 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA28. Supported peripheral buses: General.
A10JTAGSELDigital_IOSignal terminal JTAGSEL (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: JTAGSEL. Supported peripheral buses: SWD/JTAG.
B1PD31Digital_IOSignal terminal PD31 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD31. Supported peripheral buses: General.
B2PB13Digital_IOSignal terminal PB13 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
B3VDDUTMICPower_InPrimary positive power supply input (VDDUTMIC) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
B4HSDPDigital_IOSignal terminal HSDP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: HSDP. Supported peripheral buses: General.
B5PD3Digital_IOSignal terminal PD3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
B6PD6Digital_IOSignal terminal PD6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
B7PD8Digital_IOSignal terminal PD8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
B8PD9Digital_IOSignal terminal PD9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
B9PB4Digital_IOSignal terminal PB4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B10PD15Digital_IOSignal terminal PD15 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
C1PD0Digital_IOSignal terminal PD0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
C2VDDINPower_InPrimary positive power supply input (VDDIN) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
C3VDDOUTPower_InPrimary positive power supply input (VDDOUT) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
C4GNDPLLUSBGND0V electrical ground return terminal (GNDPLLUSB) for internal core logic, I/O drivers, and analog sub-blocks.
C5VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
C6VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
C7PA30Digital_IOSignal terminal PA30 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA30. Supported peripheral buses: General.
C8PB5Digital_IOSignal terminal PB5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
C9PD10Digital_IOSignal terminal PD10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
C10PA1Digital_IOSignal terminal PA1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
D1VREFPAnalogSignal terminal VREFP (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: VREFP. Supported peripheral buses: General.
D2PD1Digital_IOSignal terminal PD1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D3VREFNAnalogSignal terminal VREFN (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: VREFN. Supported peripheral buses: General.
D4GNDANAGND0V electrical ground return terminal (GNDANA) for internal core logic, I/O drivers, and analog sub-blocks.
D5PD5Digital_IOSignal terminal PD5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
D6VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
D7VDDPLLPower_InPrimary positive power supply input (VDDPLL) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
D8PA0Digital_IOSignal terminal PA0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
D9PD11Digital_IOSignal terminal PD11 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
D10PA2Digital_IOSignal terminal PA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
E1PB0Digital_IOSignal terminal PB0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
E2PB1Digital_IOSignal terminal PB1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
E3PD2Digital_IOSignal terminal PD2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
E4GNDPLLGND0V electrical ground return terminal (GNDPLL) for internal core logic, I/O drivers, and analog sub-blocks.
E5VDDUTMIIPower_InPrimary positive power supply input (VDDUTMII) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
E6VDDPLLU SBPower_InPrimary positive power supply input (VDDPLLU SB) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
E7GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
E8PD13Digital_IOSignal terminal PD13 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
E9PB7Digital_IOSignal terminal PB7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
E10PD12Digital_IOSignal terminal PD12 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
F1PA19Digital_IOSignal terminal PA19 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA19. Supported peripheral buses: General.
F2PA20Digital_IOSignal terminal PA20 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA20. Supported peripheral buses: General.
F3VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
F4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
F5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
F6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
F7TSTDigital_IOSignal terminal TST (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TST. Supported peripheral buses: General.
F8PB12Digital_IOSignal terminal PB12 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
F9PA3Digital_IOSignal terminal PA3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
F10PD14Digital_IOSignal terminal PD14 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
G1PA17Digital_IOSignal terminal PA17 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA17. Supported peripheral buses: General.
G2PA18Digital_IOSignal terminal PA18 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PA18. Supported peripheral buses: General.
G3PD26Digital_IOSignal terminal PD26 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD26. Supported peripheral buses: General.
G4PD24Digital_IOSignal terminal PD24 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PD24. Supported peripheral buses: General.
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