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DS1307ZN-778/HG (DIP-8) — Symbol, Footprint IPC-7351B & 3D STEP Model

DS1307ZN-778/HG

HGSEMIID: C54814881DIP-8 · 8 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · DS1307ZN-778/HG (DIP-8)1X12X23VBAT4GND8Vcc7SQW/OUT6SCL5SDAGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.810.25.10-5.1-10.2mm
2. 2D FOOTPRINT
12345678E=6.35mm · Pitch e=2.54mmD=9.62mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 6.35mm × 9.62mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1X1I/OMultiplexed I/O & Peripheral Pin X1 (General)
2X2I/OMultiplexed I/O & Peripheral Pin X2 (General)
3VBATPowerPower Supply Input (VBAT — 4.5V to 5.5V)
4GNDGNDGround Reference Pin (GND)
5SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
6SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
7SQW/OUTI/OMultiplexed I/O & Peripheral Pin SQW/OUT (General)
8VccPowerPower Supply Input (Vcc — 4.5V to 5.5V)
PIN 1 X1
I/O
Multiplexed I/O & Peripheral Pin X1 (General)
Design note: Signal terminal X1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: X1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: DS1307ZN-778/HG (HGSEMI · DIP-8)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
DS1307ZN-778/HG (DIP-8) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
DS1307ZN-778/HG (DIP-8) - 2. Standard Pinout (Top View)
True package pinout (8 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
DS1307ZN-778/HG (DIP-8) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
DS1307ZN-778/HG (DIP-8) - 4. Package Dimensions (D×E×A)
DIP-8 · 6.35×9.62mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
DS1307ZN-778/HG (DIP-8) - 5. Recommended Land Pattern
IPC-7351B Footprint (8 Pads)Expand ›
6. Application SchematicSCHEMATIC
DS1307ZN-778/HG (DIP-8) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for DS1307
P1 · p01_fig01EXACT PACKAGE
DS1307ZN-778/HG (DIP-8) — DIP-8
DIP-8
P1 · p01_fig02EXACT PACKAGE
DS1307ZN-778/HG (DIP-8) — SOP-8
SOP-8
P12 · p12_fig01EXACT PACKAGE
DS1307ZN-778/HG (DIP-8) — SOP-8
SOP-8
P1 · p01_fig01P1
DS1307ZN-778/HG (DIP-8) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig012707×1637px
DS1307ZN-778/HG (DIP-8) — 图1 内部功能框图
图1 内部功能框图
P6 · p06_fig012700×852px
DS1307ZN-778/HG (DIP-8) — 图3 时序图
图3 时序图
P9 · p09_fig012703×1098px
DS1307ZN-778/HG (DIP-8) — 图5 I2 C 串行总线上的数据传输
图5 I2 C 串行总线上的数据传输
P12 · p12_fig01P12
DS1307ZN-778/HG (DIP-8) — Datasheet Page 12 (p12_fig01)
Datasheet Page 12 (p12_fig01)
P13 · p13_fig01973×493px
DS1307ZN-778/HG (DIP-8) — C1 C
C1 C
P12 · p12_fig02All Packages in PDF
DS1307ZN-778/HG (DIP-8) — http://www.hgsemi.com.cn VER:V1.1 12 / 15
http://www.hgsemi.com.cn VER:V1.1 12 / 15
P13 · p13_fig02All Packages in PDF
DS1307ZN-778/HG (DIP-8) — DFN-8 3*3_0.65 Pin spacing
DFN-8 3*3_0.65 Pin spacing

Technical Specifications & Part Details (DS1307ZN-778/HG)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:DS1307ZN-778/HG (DIP-8) is a 8-pin standard electronic & interconnect component featuring a 9.62 × 6.35 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 4.5V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
4.5V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
768kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.62 × 6.35 × 4.20 mm (A1=0.00 mm)
Package family: DIP (DIP-8)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol8 auto-grouped pins
OK
IPC-7351B Land Pattern8 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (DIP-8)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.62 × 6.35 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
8P / 8Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
DIP-8
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — DS1307ZN-778/HG (DIP-8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of DS1307ZN-778/HG (DIP-8)?

Manufactured by HGSEMI, the DS1307ZN-778/HG is housed in a DIP-8 package with 8 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 4.5V to 5.5V. Key pins include: 1 (X1: Multiplexed I/O & Peripheral Pin X1 (General)), 2 (X2: Multiplexed I/O & Peripheral Pin X2 (General)), 3 (VBAT: Power Supply Input (VBAT — 4.5V to 5.5V)), 4 (GND: Ground Reference Pin (GND)), 5 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 6 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)).

What are the IPC-7351B PCB Footprint dimensions for DS1307ZN-778/HG?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DS1307ZN-778/HG (DIP-8) has a nominal body envelope of 6.35 × 9.62 mm, pitch e = 2.54 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DS1307ZN-778/HG?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DS1307ZN-778/HG (HGSEMI, DIP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & DS1307 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1X1Digital_IOSignal terminal X1 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: X1. Supported peripheral buses: General.
2X2Digital_IOSignal terminal X2 (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: X2. Supported peripheral buses: General.
3VBATPower_InPrimary positive power supply input (VBAT) operating in the 4.5V to 5.5V domain (Max rating: 5.5V).
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5SDADigital_IOSignal terminal SDA (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
6SCLDigital_IOSignal terminal SCL (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
7SQW/OUTDigital_IOSignal terminal SQW/OUT (I/O, 4.5V to 5.5V domain). Multiplexed alternate functions: SQW/OUT. Supported peripheral buses: General.
8VccPower_InPrimary positive power supply input (Vcc) operating in the 4.5V to 5.5V domain (Max rating: 5.5V).
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