Mechanical Dimensions & Land Pattern (QFN-13F(2x2))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-13F(2x2) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH271J (QFN-13F(2x2))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH271J (QFN-13F(2x2))?
Manufactured by WCH, the CH271J is housed in a QFN-13F(2x2) package with 13 pins and a 0.40 mm lead pitch. Key pins include: 1 (AI: Multiplexed I/O & Peripheral Pin AI (General)), 2 (AO: Multiplexed I/O & Peripheral Pin AO (General)), 3 (PWM1: Multiplexed I/O & Peripheral Pin PWM1 (PWM)), 4 (PWM2: Multiplexed I/O & Peripheral Pin PWM2 (PWM)), 5 (PWME: Multiplexed I/O & Peripheral Pin PWME (PWM)), 6 (GND: Ground Reference Pin (GND)).
What are the IPC-7351B PCB Footprint dimensions for CH271J?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH271J (QFN-13F(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.40 mm, and 13 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH271J?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH271J (WCH, QFN-13F(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (13 pins) & CH271 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | AI | Digital_IO | Signal terminal AI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AI. Supported peripheral buses: General. |
| 2 | AO | Digital_IO | Signal terminal AO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AO. Supported peripheral buses: General. |
| 3 | PWM1 | Digital_IO | Signal terminal PWM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM1. Supported peripheral buses: PWM. |
| 4 | PWM2 | Digital_IO | Signal terminal PWM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM2. Supported peripheral buses: PWM. |
| 5 | PWME | Digital_IO | Signal terminal PWME (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWME. Supported peripheral buses: PWM. |
| 6 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 7 | SW2 | Digital_IO | Signal terminal SW2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SW2. Supported peripheral buses: PWM. |
| 8 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 10 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 11 | SW1 | Digital_IO | Signal terminal SW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SW1. Supported peripheral buses: PWM. |
| 12 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 13 | CSO | Digital_IO | Signal terminal CSO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CSO. Supported peripheral buses: General. |