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CH319M (QFN-48(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH319M

WCHID: C52722440QFN-48(5x5) · 49 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH319M (QFN-48(5x5))1P2_HSxx_2P2_HSxx_3P2_SS_TXA4P2_SS_TXB5P2_SS_RXA6P2_SSxxx_7VDD128VDD339VDD510VSW11CFG12IO213IO114IO1615MODE/LED_P416IO3_LEDP317LED_LINK BC 18RESET#19XO20XI21UP_P1HSxx__22IO1123UP_P1_SS_TXB24UP_P1_SS_TXA25P1_VDD1249GND48P3_HSxx_47P3_HSxx_46P3_SSxxx_45IO4544IO4443P3_SS_TXA42P3_SS_TXB41IO4140P4_HSxx_39P4_SSxxx_38P4_SSxxx_37P4_VDD1236P4_SS_TXA35P4_SS_TXB34IO3433PX_SSxxx_32PX_VDD1231PX_SS_TXA30PX_SS_TXB29PX_HSxx_28PX_HSxx_27IO4726UP_P1SSxxx__Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910252627282930313233342423222120191817161514131211484746454443424140393837363549E=5.00mm · Pitch e=0.35mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P2_HSxx_I/OMultiplexed I/O & Peripheral Pin P2_HSxx_ (General)
2P2_HSxx_I/OMultiplexed I/O & Peripheral Pin P2_HSxx_ (General)
3P2_SS_TXAI/OMultiplexed I/O & Peripheral Pin P2_SS_TXA (General)
4P2_SS_TXBI/OMultiplexed I/O & Peripheral Pin P2_SS_TXB (General)
5P2_SS_RXAI/OMultiplexed I/O & Peripheral Pin P2_SS_RXA (General)
6P2_SSxxx_I/OMultiplexed I/O & Peripheral Pin P2_SSxxx_ (General)
7VDD12PowerPower Supply Input (VDD12 — 3.3V / 5.0V Standard Logic)
8VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
9VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
10VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
11CFGI/OMultiplexed I/O & Peripheral Pin CFG (General)
12IO2I/OMultiplexed I/O & Peripheral Pin IO2 (General)
13IO1I/OMultiplexed I/O & Peripheral Pin IO1 (General)
14IO16I/OGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15MODE/LED_P4I/OMultiplexed I/O & Peripheral Pin MODE/LED_P4 (General)
16IO3_LEDP3I/OMultiplexed I/O & Peripheral Pin IO3_LEDP3 (General)
17LED_LINK BC EN#_I/OMultiplexed I/O & Peripheral Pin LED_LINK BC EN#_ (General)
18RESET#ISystem Enable & Hardware Reset (RESET#)
19XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
20XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
21UP_P1HSxx__I/OMultiplexed I/O & Peripheral Pin UP_P1HSxx__ (General)
22IO11I/OGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23UP_P1_SS_TXBI/OMultiplexed I/O & Peripheral Pin UP_P1_SS_TXB (General)
24UP_P1_SS_TXAI/OMultiplexed I/O & Peripheral Pin UP_P1_SS_TXA (General)
25P1_VDD12PowerPower Supply Input (P1_VDD12 — 3.3V / 5.0V Standard Logic)
26UP_P1SSxxx__I/OMultiplexed I/O & Peripheral Pin UP_P1SSxxx__ (General)
27IO47I/OGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28PX_HSxx_I/OMultiplexed I/O & Peripheral Pin PX_HSxx_ (General)
29PX_HSxx_I/OMultiplexed I/O & Peripheral Pin PX_HSxx_ (General)
30PX_SS_TXBI/OMultiplexed I/O & Peripheral Pin PX_SS_TXB (General)
31PX_SS_TXAI/OMultiplexed I/O & Peripheral Pin PX_SS_TXA (General)
32PX_VDD12PowerPower Supply Input (PX_VDD12 — 3.3V / 5.0V Standard Logic)
33PX_SSxxx_I/OMultiplexed I/O & Peripheral Pin PX_SSxxx_ (General)
34IO34I/OGeneral Purpose Digital I/O Pin IO34
35P4_SS_TXBI/OMultiplexed I/O & Peripheral Pin P4_SS_TXB (General)
36P4_SS_TXAI/OMultiplexed I/O & Peripheral Pin P4_SS_TXA (General)
37P4_VDD12PowerPower Supply Input (P4_VDD12 — 3.3V / 5.0V Standard Logic)
38P4_SSxxx_I/OMultiplexed I/O & Peripheral Pin P4_SSxxx_ (General)
39P4_SSxxx_I/OMultiplexed I/O & Peripheral Pin P4_SSxxx_ (General)
40P4_HSxx_I/OMultiplexed I/O & Peripheral Pin P4_HSxx_ (General)
41IO41I/OGeneral Purpose Digital I/O Pin IO41
42P3_SS_TXBI/OMultiplexed I/O & Peripheral Pin P3_SS_TXB (General)
43P3_SS_TXAI/OMultiplexed I/O & Peripheral Pin P3_SS_TXA (General)
44IO44I/OGeneral Purpose Digital I/O Pin IO44
45IO45I/OGeneral Purpose Digital I/O Pin IO45
46P3_SSxxx_I/OMultiplexed I/O & Peripheral Pin P3_SSxxx_ (General)
47P3_HSxx_I/OMultiplexed I/O & Peripheral Pin P3_HSxx_ (General)
48P3_HSxx_I/OMultiplexed I/O & Peripheral Pin P3_HSxx_ (General)
49GNDGNDExposed Thermal & Ground Pad (GND)
PIN 1 P2_HSxx_
I/O
Multiplexed I/O & Peripheral Pin P2_HSxx_ (General)
Design note: Signal terminal P2_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HSxx_. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH319M (WCH · QFN-48(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH319M (QFN-48(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH319M (QFN-48(5x5)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH319M (QFN-48(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH319M (QFN-48(5x5)) - 4. Package Dimensions (D×E×A)
QFN-48(5x5) · 5.00×5.00mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH319M (QFN-48(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH319M (QFN-48(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH319
P3 · p03_fig01EXACT PACKAGE
CH319M (QFN-48(5x5)) — V1.1 3
V1.1 3
P1 · p01_fig011506×705px
CH319M (QFN-48(5x5)) — 图1-1 CH319M 变压器隔离应用框图 图1-2 CH319M 光纤延长U3 设备应用框图
图1-1 CH319M 变压器隔离应用框图 图1-2 CH319M 光纤延长U3 设备应用框图
P1 · p01_fig021700×703px
CH319M (QFN-48(5x5)) — 图1-2 CH319M 光纤延长U3 设备应用框图
图1-2 CH319M 光纤延长U3 设备应用框图
P2 · p02_fig011677×946px
CH319M (QFN-48(5x5)) — 图1-3 CH319M+CH319X 光纤延长U3+U2 设备应用框图 2、特点
图1-3 CH319M+CH319X 光纤延长U3+U2 设备应用框图 2、特点
P17 · p17_fig011738×2368px
CH319M (QFN-48(5x5)) — 图8-1 CH319M 变压器隔离应用参考电路图
图8-1 CH319M 变压器隔离应用参考电路图
P17 · p17_fig01P17
CH319M (QFN-48(5x5)) — Datasheet Page 17 (p17_fig01)
Datasheet Page 17 (p17_fig01)
P19 · p19_fig011657×1319px
CH319M (QFN-48(5x5)) — 图8-2 CH319M 光纤延长U3 设备方案应用参考电路图
图8-2 CH319M 光纤延长U3 设备方案应用参考电路图
P19 · p19_fig021686×1849px
CH319M (QFN-48(5x5)) — V1.1 19
V1.1 19
P20 · p20_fig011654×1692px
CH319M (QFN-48(5x5)) — 图8-3 CH319M+CH319X 光纤延长U3+U2 设备方案应用参考电路图 DPX_SS_RXA PX_SS_RXA 66
图8-3 CH319M+CH319X 光纤延长U3+U2 设备方案应用参考电路图 DPX_SS_RXA PX_SS_RXA 66

Technical Specifications & Part Details (CH319M)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH319M (QFN-48(5x5)) is a 48-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48(5x5))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.35mm
Pad Size (W × L)Level B
0.16 × 0.75 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH319M (QFN-48(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH319M (QFN-48(5x5))?

Manufactured by WCH, the CH319M is housed in a QFN-48(5x5) package with 49 pins and a 0.35 mm lead pitch. Key pins include: 1 (P2_HSxx_: Multiplexed I/O & Peripheral Pin P2_HSxx_ (General)), 2 (P2_HSxx_: Multiplexed I/O & Peripheral Pin P2_HSxx_ (General)), 3 (P2_SS_TXA: Multiplexed I/O & Peripheral Pin P2_SS_TXA (General)), 4 (P2_SS_TXB: Multiplexed I/O & Peripheral Pin P2_SS_TXB (General)), 5 (P2_SS_RXA: Multiplexed I/O & Peripheral Pin P2_SS_RXA (General)), 6 (P2_SSxxx_: Multiplexed I/O & Peripheral Pin P2_SSxxx_ (General)).

What are the IPC-7351B PCB Footprint dimensions for CH319M?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH319M (QFN-48(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.35 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH319M?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH319M (WCH, QFN-48(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & CH319 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P2_HSxx_Digital_IOSignal terminal P2_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HSxx_. Supported peripheral buses: General.
2P2_HSxx_Digital_IOSignal terminal P2_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HSxx_. Supported peripheral buses: General.
3P2_SS_TXADigital_IOSignal terminal P2_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXA. Supported peripheral buses: General.
4P2_SS_TXBDigital_IOSignal terminal P2_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXB. Supported peripheral buses: General.
5P2_SS_RXADigital_IOSignal terminal P2_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_RXA. Supported peripheral buses: General.
6P2_SSxxx_Digital_IOSignal terminal P2_SSxxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SSxxx_. Supported peripheral buses: General.
7VDD12Power_InPrimary positive power supply input (VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
11CFGDigital_IOSignal terminal CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG. Supported peripheral buses: General.
12IO2Digital_IOSignal terminal IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO2. Supported peripheral buses: General.
13IO1Digital_IOSignal terminal IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO1. Supported peripheral buses: General.
14IO16Digital_IOGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15MODE/LED_P4Digital_IOSignal terminal MODE/LED_P4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MODE/LED_P4. Supported peripheral buses: General.
16IO3_LEDP3Digital_IOSignal terminal IO3_LEDP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO3_LEDP3. Supported peripheral buses: General.
17LED_LINK BC EN#_Digital_IOSignal terminal LED_LINK BC EN#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_LINK BC EN#_. Supported peripheral buses: General.
18RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
19XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
20XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
21UP_P1HSxx__Digital_IOSignal terminal UP_P1HSxx__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_P1HSxx__. Supported peripheral buses: General.
22IO11Digital_IOGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23UP_P1_SS_TXBDigital_IOSignal terminal UP_P1_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_P1_SS_TXB. Supported peripheral buses: General.
24UP_P1_SS_TXADigital_IOSignal terminal UP_P1_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_P1_SS_TXA. Supported peripheral buses: General.
25P1_VDD12Power_InPrimary positive power supply input (P1_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26UP_P1SSxxx__Digital_IOSignal terminal UP_P1SSxxx__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_P1SSxxx__. Supported peripheral buses: General.
27IO47Digital_IOGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28PX_HSxx_Digital_IOSignal terminal PX_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PX_HSxx_. Supported peripheral buses: General.
29PX_HSxx_Digital_IOSignal terminal PX_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PX_HSxx_. Supported peripheral buses: General.
30PX_SS_TXBDigital_IOSignal terminal PX_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PX_SS_TXB. Supported peripheral buses: General.
31PX_SS_TXADigital_IOSignal terminal PX_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PX_SS_TXA. Supported peripheral buses: General.
32PX_VDD12Power_InPrimary positive power supply input (PX_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
33PX_SSxxx_Digital_IOSignal terminal PX_SSxxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PX_SSxxx_. Supported peripheral buses: General.
34IO34Digital_IOGeneral Purpose Digital I/O Pin IO34
35P4_SS_TXBDigital_IOSignal terminal P4_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXB. Supported peripheral buses: General.
36P4_SS_TXADigital_IOSignal terminal P4_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXA. Supported peripheral buses: General.
37P4_VDD12Power_InPrimary positive power supply input (P4_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
38P4_SSxxx_Digital_IOSignal terminal P4_SSxxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SSxxx_. Supported peripheral buses: General.
39P4_SSxxx_Digital_IOSignal terminal P4_SSxxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SSxxx_. Supported peripheral buses: General.
40P4_HSxx_Digital_IOSignal terminal P4_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HSxx_. Supported peripheral buses: General.
41IO41Digital_IOGeneral Purpose Digital I/O Pin IO41
42P3_SS_TXBDigital_IOSignal terminal P3_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXB. Supported peripheral buses: General.
43P3_SS_TXADigital_IOSignal terminal P3_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXA. Supported peripheral buses: General.
44IO44Digital_IOGeneral Purpose Digital I/O Pin IO44
45IO45Digital_IOGeneral Purpose Digital I/O Pin IO45
46P3_SSxxx_Digital_IOSignal terminal P3_SSxxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SSxxx_. Supported peripheral buses: General.
47P3_HSxx_Digital_IOSignal terminal P3_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HSxx_. Supported peripheral buses: General.
48P3_HSxx_Digital_IOSignal terminal P3_HSxx_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HSxx_. Supported peripheral buses: General.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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