DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the DSPIC33EP32GP502-I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI/RA2: Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA2 (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for DSPIC33EP32GP502-I/MM?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DSPIC33EP32GP502-I/MM?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DSPIC33EP32GP502-I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	IO1	I/O	General Purpose Digital I/O Pin IO1
2	IO2	I/O	General Purpose Digital I/O Pin IO2
3	3V3	Power	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	NC	No Connect (Leave Floating)
5	VSS	GND	Ground Reference Pin (VSS)
6	OSC1/CLKI/RA2	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA2 (RTC/CLK)
7	OSC2/CLKO/RA3	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO/RA3 (RTC/CLK)
8	RP36/RB4	I/O	Multiplexed I/O & Peripheral Pin RP36/RB4 (General)
9	CVREF2O/RP20/T1CK/RA4	Analog	Multiplexed I/O & Peripheral Pin CVREF2O/RP20/T1CK/RA4 (General)
10	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
11	PGED2/ASDA2/RP37/RB5	I/O	Multiplexed I/O & Peripheral Pin PGED2/ASDA2/RP37/RB5 (General)
12	PGEC2/ASCL2/RP38/RB6	I/O	Multiplexed I/O & Peripheral Pin PGEC2/ASCL2/RP38/RB6 (General)
13	SCK1/RP39/INT0/RB7	I/O	Multiplexed I/O & Peripheral Pin SCK1/RP39/INT0/RB7 (SPI)
14	IO16	I/O	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	I/O	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	VSS	GND	Ground Reference Pin (VSS)
17	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
18	TDO/RP42/RB10	I/O	Multiplexed I/O & Peripheral Pin TDO/RP42/RB10 (General)
19	TDI/RP43/RB11	I/O	Multiplexed I/O & Peripheral Pin TDI/RP43/RB11 (General)
20	RPI44/RB12	I/O	Multiplexed I/O & Peripheral Pin RPI44/RB12 (General)
21	RPI45/CTPLS/RB13	I/O	Multiplexed I/O & Peripheral Pin RPI45/CTPLS/RB13 (General)
22	RPI46/T3CK/RB14	I/O	Multiplexed I/O & Peripheral Pin RPI46/T3CK/RB14 (General)
23	RPI47/T5CK/RB15	I/O	Multiplexed I/O & Peripheral Pin RPI47/T5CK/RB15 (General)
24	AVSS	GND	Ground Reference Pin (AVSS)
25	AVDD	Power	Power Supply Input (AVDD — 3.0V to 3.6V)
26	MCLR#	I/O	Multiplexed I/O & Peripheral Pin MCLR# (General)
27	AN0/OA2OUT/RA0	I/O	Multiplexed I/O & Peripheral Pin AN0/OA2OUT/RA0 (General)
28	AN1/C2IN1+/RA1	I/O	Multiplexed I/O & Peripheral Pin AN1/C2IN1+/RA1 (General)
29	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 IO1

I/O

General Purpose Digital I/O Pin IO1

Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for DSPIC33EP32G

P1 · p01_fig01377×201px

16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, Op Amps and Advanced Analog

P25 · p25_fig011777×1658px

FIGURE 1-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X BLOCK DIAGRAM

P32 · p32_fig011297×980px

FIGURE 2-4: BOOST CONVERTER IMPLEMENTATION

P34 · p34_fig011469×1006px

FIGURE 2-7: INTERLEAVED PFC

P34 · p34_fig021162×699px

FIGURE 2-8: BEMF VOLTAGE MEASURED USING THE ADC MODULE

P34 · p34_fig02P34

Datasheet Page 34 (p34_fig02)

P119 · p119_fig011777×976px

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

P479 · p479_fig011777×2599px

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X

P126 · p126_fig01874×366px

DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) — MOV 0xFF00, W0 ; Configure PORTB<15:8> ; as inputs MOV W0, TRISB ; and PORTB<7:0> ; as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction [QFN-44-EP(8x8)]

MOV 0xFF00, W0 ; Configure PORTB<15:8> ; as inputs MOV W0, TRISB ; and PORTB<7:0> ; as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction [QFN-44-EP(8x8)]

P128 · p128_fig01867×999px

FIGURE 10-2: REMAPPABLE INPUT FOR U1RX [QFN-44-EP(8x8)]

P360 · p360_fig011784×2735px

RECOMMENDED_FOOTPRINT — dsPIC33EP32GS504T-I/ML (QFN-44-EP(8x8))

P368 · p368_fig011778×2735px

PACKAGE_DIMENSIONS — dsPIC33EP32GS504T-I/ML (QFN-44-EP(8x8))

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (DSPIC33EP32GP502-I/MM)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +85°C with integrated UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

140 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 1.00 mm (A1=0.03 mm)

Package family: QFN (QFN-28-EP(6x6))

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — DSPIC33EP32G (3)

Select package variant or sibling MPN sharing this datasheet

QFN-28-EP(6x6) · 29P

DSPIC33EP32GP502-I/MM

MICROCHIP·QFN-28-EP(6x6)

IPC-7351B

29P6.0×6.0×1.00mmP=0.65mm

DSPIC33EP32G (QFN-28-EP(6x6))

QFN-44-EP(8x8) · 45P

dsPIC33EP32GS504T-I/ML

MICROCHIP·QFN-44-EP(8x8)

IPC-7351B

45P8.0×8.0×1.00mmP=0.5mm

DSPIC33EP32G (QFN-44-EP(8x8))

TQFP-48-EP(7x7) · 48P

dsPIC33EP32GS505T-I/PT

MICROCHIP·TQFP-48-EP(7x7)

IPC-7351B

48P7.0×7.0×1.20mmP=0.5mm

DSPIC33EP32G (TQFP-48-EP(7x7))

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-28-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the DSPIC33EP32GP502-I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (VSS: Ground Reference Pin (VSS)), 6 (OSC1/CLKI/RA2: Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA2 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for DSPIC33EP32GP502-I/MM?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DSPIC33EP32GP502-I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DSPIC33EP32GP502-I/MM?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DSPIC33EP32GP502-I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & DSPIC33EP32G Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	IO1	Digital_IO	General Purpose Digital I/O Pin IO1
2	IO2	Digital_IO	General Purpose Digital I/O Pin IO2
3	3V3	Power_In	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	No_Connect	No Connect (Leave Floating)
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	OSC1/CLKI/RA2	Digital_IO	Signal terminal OSC1/CLKI/RA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/RA2. Supported peripheral buses: RTC/CLK.
7	OSC2/CLKO/RA3	Digital_IO	Signal terminal OSC2/CLKO/RA3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC2/CLKO/RA3. Supported peripheral buses: RTC/CLK.
8	RP36/RB4	Digital_IO	Signal terminal RP36/RB4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RP36/RB4. Supported peripheral buses: General.
9	CVREF2O/RP20/T1CK/RA4	Analog	Signal terminal CVREF2O/RP20/T1CK/RA4 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: CVREF2O/RP20/T1CK/RA4. Supported peripheral buses: General.
10	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
11	PGED2/ASDA2/RP37/RB5	Digital_IO	Signal terminal PGED2/ASDA2/RP37/RB5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PGED2/ASDA2/RP37/RB5. Supported peripheral buses: General.
12	PGEC2/ASCL2/RP38/RB6	Digital_IO	Signal terminal PGEC2/ASCL2/RP38/RB6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PGEC2/ASCL2/RP38/RB6. Supported peripheral buses: General.
13	SCK1/RP39/INT0/RB7	Digital_IO	Signal terminal SCK1/RP39/INT0/RB7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SCK1/RP39/INT0/RB7. Supported peripheral buses: SPI.
14	IO16	Digital_IO	GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15	IO17	Digital_IO	GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17	VCAP	Digital_IO	Signal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
18	TDO/RP42/RB10	Digital_IO	Signal terminal TDO/RP42/RB10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDO/RP42/RB10. Supported peripheral buses: General.
19	TDI/RP43/RB11	Digital_IO	Signal terminal TDI/RP43/RB11 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TDI/RP43/RB11. Supported peripheral buses: General.
20	RPI44/RB12	Digital_IO	Signal terminal RPI44/RB12 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI44/RB12. Supported peripheral buses: General.
21	RPI45/CTPLS/RB13	Digital_IO	Signal terminal RPI45/CTPLS/RB13 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI45/CTPLS/RB13. Supported peripheral buses: General.
22	RPI46/T3CK/RB14	Digital_IO	Signal terminal RPI46/T3CK/RB14 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI46/T3CK/RB14. Supported peripheral buses: General.
23	RPI47/T5CK/RB15	Digital_IO	Signal terminal RPI47/T5CK/RB15 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RPI47/T5CK/RB15. Supported peripheral buses: General.
24	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
25	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
26	MCLR#	Digital_IO	Signal terminal MCLR# (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
27	AN0/OA2OUT/RA0	Digital_IO	Signal terminal AN0/OA2OUT/RA0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN0/OA2OUT/RA0. Supported peripheral buses: General.
28	AN1/C2IN1+/RA1	Digital_IO	Signal terminal AN1/C2IN1+/RA1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AN1/C2IN1+/RA1. Supported peripheral buses: General.
29	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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