![MCP6072T-E/MNY (TDFN-8-EP(2x3)) — 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] - Note: For the most current package drawings, please see the Microchip Packaging Specification located at - http:/www.microchip.com/packaging | © 2010 Microchip Technology In](/api/v1/assets/C511309/extracted/figures/p31_fig01.png)
Mechanical Dimensions & Land Pattern (TDFN-8-EP(2x3))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TDFN-8-EP(2x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — MCP6072T-E/MNY (TDFN-8-EP(2x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of MCP6072T-E/MNY (TDFN-8-EP(2x3))?
Manufactured by MICROCHIP, the MCP6072T-E/MNY is housed in a TDFN-8-EP(2x3) package with 9 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V to 6.0V. Key pins include: 1 (V V OUT, OUTA: Multiplexed I/O & Peripheral Pin V V OUT, OUTA (General)), 2 (V V IN–, INA–: Multiplexed I/O & Peripheral Pin V V IN–, INA– (General)), 3 (V IN+ V INA+ ,: Multiplexed I/O & Peripheral Pin V IN+ V INA+ , (General)), 4 (VSS: Ground Reference Pin (VSS)), 5 (V INB+: Multiplexed I/O & Peripheral Pin V INB+ (General)), 6 (V INB–: Multiplexed I/O & Peripheral Pin V INB– (General)).
What are the IPC-7351B PCB Footprint dimensions for MCP6072T-E/MNY?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP6072T-E/MNY (TDFN-8-EP(2x3)) has a nominal body envelope of 2.00 × 3.00 mm, pitch e = 0.50 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 1.60 × 1.60 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP6072T-E/MNY?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP6072T-E/MNY (MICROCHIP, TDFN-8-EP(2x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (9 pins) & MCP6072 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | V V OUT, OUTA | Digital_IO | Signal terminal V V OUT, OUTA (I/O, 1.8V to 6.0V domain). Multiplexed alternate functions: V V OUT, OUTA. Supported peripheral buses: General. |
| 2 | V V IN–, INA– | Digital_IO | Signal terminal V V IN–, INA– (I/O, 1.8V to 6.0V domain). Multiplexed alternate functions: V V IN–, INA–. Supported peripheral buses: General. |
| 3 | V IN+ V INA+ , | Digital_IO | Signal terminal V IN+ V INA+ , (I/O, 1.8V to 6.0V domain). Multiplexed alternate functions: V IN+ V INA+ ,. Supported peripheral buses: General. |
| 4 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 5 | V INB+ | Digital_IO | Signal terminal V INB+ (I/O, 1.8V to 6.0V domain). Multiplexed alternate functions: V INB+. Supported peripheral buses: General. |
| 6 | V INB– | Digital_IO | Signal terminal V INB– (I/O, 1.8V to 6.0V domain). Multiplexed alternate functions: V INB–. Supported peripheral buses: General. |
| 7 | V OUTB | Digital_IO | Signal terminal V OUTB (I/O, 1.8V to 6.0V domain). Multiplexed alternate functions: V OUTB. Supported peripheral buses: General. |
| 8 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 1.8V to 6.0V domain (Max rating: 6.0V). |
| 9 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |