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DSPIC30F3010-30I/SP (SPDIP-28) — Symbol, Footprint IPC-7351B & 3D STEP Model

DSPIC30F3010-30I/SP

MICROCHIPID: C511305SPDIP-28 · 28 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · DSPIC30F3010-30I/SP (SPDIP-28)1MCLR#2IO233V34AN2/SS1#/CN45AN3/INDX/CN56AN4/QEA/IC7/7AN5/QEB/IC8/8VSS9OSC1/CLKI10OSC2/CLKO/RC11IO612IO713VDD14EMUD2/OC2/IC28AVDD27AVSS26PWM1L/RE025PWM1H/RE124PWM2L/RE223PWM2H/RE322PWM3L/RE421PWM3H/RE520VDD19VSS18IO1917IO816IO1815EMUC2/OC1/ICGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
15141613272262524232217181920121110934567821281E=34.70mm · Pitch e=0.50mmD=7.20mm-27-25-23-21-19-17-15-13-11-9-7-5-3-11357911131517192123252714121086420-2-4-6-8-10-12-14mm
3. 3D CAD MODEL
Package Body: 34.70mm × 7.20mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MCLR#I/OMultiplexed I/O & Peripheral Pin MCLR# (General)
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4AN2/SS1#/CN4/RB2I/OMultiplexed I/O & Peripheral Pin AN2/SS1#/CN4/RB2 (General)
5AN3/INDX/CN5/RB3I/OMultiplexed I/O & Peripheral Pin AN3/INDX/CN5/RB3 (General)
6AN4/QEA/IC7/CN6/RB4I/OMultiplexed I/O & Peripheral Pin AN4/QEA/IC7/CN6/RB4 (General)
7AN5/QEB/IC8/CN7/RB5I/OMultiplexed I/O & Peripheral Pin AN5/QEB/IC8/CN7/RB5 (General)
8VSSGNDGround Reference Pin (VSS)
9OSC1/CLKII/OMultiplexed I/O & Peripheral Pin OSC1/CLKI (RTC/CLK)
10OSC2/CLKO/RC15I/OMultiplexed I/O & Peripheral Pin OSC2/CLKO/RC15 (RTC/CLK)
11IO6I/OGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
14EMUD2/OC2/IC2/INT2/RD1I/OMultiplexed I/O & Peripheral Pin EMUD2/OC2/IC2/INT2/RD1 (General)
15EMUC2/OC1/IC1/INT1/RD0I/OMultiplexed I/O & Peripheral Pin EMUC2/OC1/IC1/INT1/RD0 (General)
16IO18I/OGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8I/OGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19I/OGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19VSSGNDGround Reference Pin (VSS)
20VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
21PWM3H/RE5I/OMultiplexed I/O & Peripheral Pin PWM3H/RE5 (PWM)
22PWM3L/RE4I/OMultiplexed I/O & Peripheral Pin PWM3L/RE4 (PWM)
23PWM2H/RE3I/OMultiplexed I/O & Peripheral Pin PWM2H/RE3 (PWM)
24PWM2L/RE2I/OMultiplexed I/O & Peripheral Pin PWM2L/RE2 (PWM)
25PWM1H/RE1I/OMultiplexed I/O & Peripheral Pin PWM1H/RE1 (PWM)
26PWM1L/RE0I/OMultiplexed I/O & Peripheral Pin PWM1L/RE0 (PWM)
27AVSSGNDGround Reference Pin (AVSS)
28AVDDPowerPower Supply Input (AVDD — 3.3V / 5.0V Standard Logic)
PIN 1 MCLR#
I/O
Multiplexed I/O & Peripheral Pin MCLR# (General)
Design note: Signal terminal MCLR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 2 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: DSPIC30F3010-30I/SP (MICROCHIP · SPDIP-28)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
DSPIC30F3010-30I/SP (SPDIP-28) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
DSPIC30F3010-30I/SP (SPDIP-28) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
DSPIC30F3010-30I/SP (SPDIP-28) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
DSPIC30F3010-30I/SP (SPDIP-28) - 4. Package Dimensions (D×E×A)
SPDIP-28 · 34.70×7.20mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
DSPIC30F3010-30I/SP (SPDIP-28) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
DSPIC30F3010-30I/SP (SPDIP-28) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (2 figures · Page 1/1)
Showing 1–2 of 2 uncropped original figures for DSPIC30F3010
P21 · p21_fig011779×2522px
DSPIC30F3010-30I/SP (SPDIP-28) — © 2010 Microchip Technology Inc. DS80449D-page 21 | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In
© 2010 Microchip Technology Inc. DS80449D-page 21 | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In
P21 · p21_fig02784×283px
DSPIC30F3010-30I/SP (SPDIP-28) — ISBN: 978-1-60932-252-6
ISBN: 978-1-60932-252-6

Technical Specifications & Part Details (DSPIC30F3010-30I/SP)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:DSPIC30F3010-30I/SP (SPDIP-28) is a 28-pin standard electronic & interconnect component featuring a 34.70 × 7.20 × 2.00 mm mechanical envelope (lead pitch e = 0.00 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, I2C, ADC, PWM, RTC/CLK, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
34.70 × 7.20 × 2.00 mm (A1=0.02 mm)
Package family: OTHER (SPDIP-28)
Pin Count & Lead PitchN / e
28 Pins
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, I2C, ADC, PWM, RTC/CLK, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SPDIP-28)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
34.70 × 7.20 mm
Height (A) & Pitch (e)IPC-7351B
A=2.00mm · e=0.50mm
Pad Size (W × L)Level B
0.40 × 0.90 mm
Pins / Total PadsTopology
28P / 28Pad (CUSTOM_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SPDIP-28
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — DSPIC30F3010-30I/SP (SPDIP-28)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of DSPIC30F3010-30I/SP (SPDIP-28)?

Manufactured by MICROCHIP, the DSPIC30F3010-30I/SP is housed in a SPDIP-28 package with 28 pins and a 0.50 mm lead pitch. Key pins include: 1 (MCLR#: Multiplexed I/O & Peripheral Pin MCLR# (General)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (AN2/SS1#/CN4/RB2: Multiplexed I/O & Peripheral Pin AN2/SS1#/CN4/RB2 (General)), 5 (AN3/INDX/CN5/RB3: Multiplexed I/O & Peripheral Pin AN3/INDX/CN5/RB3 (General)), 6 (AN4/QEA/IC7/CN6/RB4: Multiplexed I/O & Peripheral Pin AN4/QEA/IC7/CN6/RB4 (General)).

What are the IPC-7351B PCB Footprint dimensions for DSPIC30F3010-30I/SP?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DSPIC30F3010-30I/SP (SPDIP-28) has a nominal body envelope of 7.20 × 34.70 mm, pitch e = 0.50 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DSPIC30F3010-30I/SP?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DSPIC30F3010-30I/SP (MICROCHIP, SPDIP-28) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & DSPIC30F3010 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MCLR#Digital_IOSignal terminal MCLR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4AN2/SS1#/CN4/RB2Digital_IOSignal terminal AN2/SS1#/CN4/RB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AN2/SS1#/CN4/RB2. Supported peripheral buses: General.
5AN3/INDX/CN5/RB3Digital_IOSignal terminal AN3/INDX/CN5/RB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AN3/INDX/CN5/RB3. Supported peripheral buses: General.
6AN4/QEA/IC7/CN6/RB4Digital_IOSignal terminal AN4/QEA/IC7/CN6/RB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AN4/QEA/IC7/CN6/RB4. Supported peripheral buses: General.
7AN5/QEB/IC8/CN7/RB5Digital_IOSignal terminal AN5/QEB/IC8/CN7/RB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AN5/QEB/IC8/CN7/RB5. Supported peripheral buses: General.
8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9OSC1/CLKIDigital_IOSignal terminal OSC1/CLKI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC1/CLKI. Supported peripheral buses: RTC/CLK.
10OSC2/CLKO/RC15Digital_IOSignal terminal OSC2/CLKO/RC15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC2/CLKO/RC15. Supported peripheral buses: RTC/CLK.
11IO6Digital_IOGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14EMUD2/OC2/IC2/INT2/RD1Digital_IOSignal terminal EMUD2/OC2/IC2/INT2/RD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EMUD2/OC2/IC2/INT2/RD1. Supported peripheral buses: General.
15EMUC2/OC1/IC1/INT1/RD0Digital_IOSignal terminal EMUC2/OC1/IC1/INT1/RD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EMUC2/OC1/IC1/INT1/RD0. Supported peripheral buses: General.
16IO18Digital_IOGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8Digital_IOGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19Digital_IOGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21PWM3H/RE5Digital_IOSignal terminal PWM3H/RE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM3H/RE5. Supported peripheral buses: PWM.
22PWM3L/RE4Digital_IOSignal terminal PWM3L/RE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM3L/RE4. Supported peripheral buses: PWM.
23PWM2H/RE3Digital_IOSignal terminal PWM2H/RE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM2H/RE3. Supported peripheral buses: PWM.
24PWM2L/RE2Digital_IOSignal terminal PWM2L/RE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM2L/RE2. Supported peripheral buses: PWM.
25PWM1H/RE1Digital_IOSignal terminal PWM1H/RE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM1H/RE1. Supported peripheral buses: PWM.
26PWM1L/RE0Digital_IOSignal terminal PWM1L/RE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM1L/RE0. Supported peripheral buses: PWM.
27AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
28AVDDPower_InPrimary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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