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PIC16LF1825-I/ST (TSSOP-14) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16LF1825-I/ST

MICROCHIPID: C50134TSSOP-14 · 14 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16LF1825-I/ST (TSSOP-14)1PIC12F1840 P2PIC16F1829 P3RA44RA3/MCLR#/VP5RC56RC47RC314VSS13RA0/ICSPDAT12RA1/ICSPCLK11RA210RC09RC18RC2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.815.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
1234567891011121314E=4.40mm · Pitch e=0.65mmD=5.00mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.40mm × 5.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (14/14)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PIC12F1840 PIC12LF1840I/OMultiplexed I/O & Peripheral Pin PIC12F1840 PIC12LF1840 (General)
2PIC16F1829 PIC16LF1829I/OMultiplexed I/O & Peripheral Pin PIC16F1829 PIC16LF1829 (General)
3RA4I/OMultiplexed I/O & Peripheral Pin RA4 (General)
4RA3/MCLR#/VPPI/OMultiplexed I/O & Peripheral Pin RA3/MCLR#/VPP (General)
5RC5I/OMultiplexed I/O & Peripheral Pin RC5 (General)
6RC4I/OMultiplexed I/O & Peripheral Pin RC4 (General)
7RC3I/OMultiplexed I/O & Peripheral Pin RC3 (General)
8RC2I/OMultiplexed I/O & Peripheral Pin RC2 (General)
9RC1I/OMultiplexed I/O & Peripheral Pin RC1 (General)
10RC0I/OMultiplexed I/O & Peripheral Pin RC0 (General)
11RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
12RA1/ICSPCLKI/OMultiplexed I/O & Peripheral Pin RA1/ICSPCLK (General)
13RA0/ICSPDATI/OMultiplexed I/O & Peripheral Pin RA0/ICSPDAT (General)
14VSSGNDGround Reference Pin (VSS)
PIN 1 PIC12F1840 PIC12LF1840
I/O
Multiplexed I/O & Peripheral Pin PIC12F1840 PIC12LF1840 (General)
Design note: Signal terminal PIC12F1840 PIC12LF1840 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIC12F1840 PIC12LF1840. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16LF1825-I/ST (MICROCHIP · TSSOP-14)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16LF1825-I/ST (TSSOP-14) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16LF1825-I/ST (TSSOP-14) - 2. Standard Pinout (Top View)
True package pinout (14 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16LF1825-I/ST (TSSOP-14) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16LF1825-I/ST (TSSOP-14) - 4. Package Dimensions (D×E×A)
TSSOP-14 · 4.40×5.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16LF1825-I/ST (TSSOP-14) - 5. Recommended Land Pattern
IPC-7351B Footprint (14 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16LF1825-I/ST (TSSOP-14) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for PIC16LF1825
P1 · p01_fig011991×2434px
PIC16LF1825-I/ST (TSSOP-14) — PIC12F/PIC16F182X Microcontrollers High Feature, Low Pin Count 8-bit MCUs
PIC12F/PIC16F182X Microcontrollers High Feature, Low Pin Count 8-bit MCUs
P1 · p01_fig02942×668px
PIC16LF1825-I/ST (TSSOP-14) — The “Green” Microcontroller
The “Green” Microcontroller
P1 · p01_fig03932×1123px
PIC16LF1825-I/ST (TSSOP-14) — PWMs with up to 4 available time bases are available to support a wide array of motor control and lighting types, such as LED and fl uorescent lighting.
PWMs with up to 4 available time bases are available to support a wide array of motor control and lighting types, such as LED and fl uorescent lighting.
P1 · p01_fig03P1
PIC16LF1825-I/ST (TSSOP-14) — Datasheet Page 1 (p01_fig03)
Datasheet Page 1 (p01_fig03)
P2 · p02_fig012040×1985px
PIC16LF1825-I/ST (TSSOP-14) — Microchip Technology Inc. • 2355 W. Chandler Blvd. • Chandler, AZ 85224-6199
Microchip Technology Inc. • 2355 W. Chandler Blvd. • Chandler, AZ 85224-6199

Technical Specifications & Part Details (PIC16LF1825-I/ST)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16LF1825-I/ST (TSSOP-14) is a 14-pin standard electronic & interconnect component featuring a 5.00 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-14)
Pin Count & Lead PitchN / e
14 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol14 auto-grouped pins
OK
IPC-7351B Land Pattern14 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-14)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
14P / 14Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-14
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16LF1825-I/ST (TSSOP-14)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16LF1825-I/ST (TSSOP-14)?

Manufactured by MICROCHIP, the PIC16LF1825-I/ST is housed in a TSSOP-14 package with 14 pins and a 0.65 mm lead pitch. Key pins include: 1 (PIC12F1840 PIC12LF1840: Multiplexed I/O & Peripheral Pin PIC12F1840 PIC12LF1840 (General)), 2 (PIC16F1829 PIC16LF1829: Multiplexed I/O & Peripheral Pin PIC16F1829 PIC16LF1829 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (RA3/MCLR#/VPP: Multiplexed I/O & Peripheral Pin RA3/MCLR#/VPP (General)), 5 (RC5: Multiplexed I/O & Peripheral Pin RC5 (General)), 6 (RC4: Multiplexed I/O & Peripheral Pin RC4 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16LF1825-I/ST?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF1825-I/ST (TSSOP-14) has a nominal body envelope of 4.40 × 5.00 mm, pitch e = 0.65 mm, and 14 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF1825-I/ST?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF1825-I/ST (MICROCHIP, TSSOP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (14 pins) & PIC16LF1825 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PIC12F1840 PIC12LF1840Digital_IOSignal terminal PIC12F1840 PIC12LF1840 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIC12F1840 PIC12LF1840. Supported peripheral buses: General.
2PIC16F1829 PIC16LF1829Digital_IOSignal terminal PIC16F1829 PIC16LF1829 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIC16F1829 PIC16LF1829. Supported peripheral buses: General.
3RA4Digital_IOSignal terminal RA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
4RA3/MCLR#/VPPDigital_IOSignal terminal RA3/MCLR#/VPP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RA3/MCLR#/VPP. Supported peripheral buses: General.
5RC5Digital_IOSignal terminal RC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
6RC4Digital_IOSignal terminal RC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
7RC3Digital_IOSignal terminal RC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
8RC2Digital_IOSignal terminal RC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
9RC1Digital_IOSignal terminal RC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
10RC0Digital_IOSignal terminal RC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
11RA2Digital_IOSignal terminal RA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
12RA1/ICSPCLKDigital_IOSignal terminal RA1/ICSPCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RA1/ICSPCLK. Supported peripheral buses: General.
13RA0/ICSPDATDigital_IOSignal terminal RA0/ICSPDAT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RA0/ICSPDAT. Supported peripheral buses: General.
14VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
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