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CH211C (QFN-16C(2x2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH211C

WCHID: C49438114QFN-16C(2x2) · 17 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH211C (QFN-16C(2x2))1SDA2SCL3ODL14ODL25CCL16CCL27HVIO8KEY9CCPDG217VSYS16VBUS15HVCP14ODH113ODH212CCH111CCH210CCPDG1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617E=2.00mm · Pitch e=0.40mmD=2.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 2.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (17/17)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
2SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
3ODL1I/OMultiplexed I/O & Peripheral Pin ODL1 (General)
4ODL2I/OMultiplexed I/O & Peripheral Pin ODL2 (General)
5CCL1I/OMultiplexed I/O & Peripheral Pin CCL1 (General)
6CCL2I/OMultiplexed I/O & Peripheral Pin CCL2 (General)
7HVIOI/OMultiplexed I/O & Peripheral Pin HVIO (General)
8KEYI/OMultiplexed I/O & Peripheral Pin KEY (General)
9CCPDG2I/OMultiplexed I/O & Peripheral Pin CCPDG2 (General)
10CCPDG1I/OMultiplexed I/O & Peripheral Pin CCPDG1 (General)
11CCH2I/OMultiplexed I/O & Peripheral Pin CCH2 (General)
12CCH1I/OMultiplexed I/O & Peripheral Pin CCH1 (General)
13ODH2I/OMultiplexed I/O & Peripheral Pin ODH2 (General)
14ODH1I/OMultiplexed I/O & Peripheral Pin ODH1 (General)
15HVCPI/OMultiplexed I/O & Peripheral Pin HVCP (General)
16VBUSPowerPower Supply Input (VBUS — 3.3V / 5.0V Standard Logic)
17VSYSI/OMultiplexed I/O & Peripheral Pin VSYS (General)
PIN 1 SDA
I/O
Multiplexed I/O & Peripheral Pin SDA (I2C)
Design note: 2线串行接口的数据输入和输出 ， 内置可控的上拉电阻
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH211C (WCH · QFN-16C(2x2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH211C (QFN-16C(2x2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH211C (QFN-16C(2x2)) - 2. Standard Pinout (Top View)
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH211C (QFN-16C(2x2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH211C (QFN-16C(2x2)) - 4. Package Dimensions (D×E×A)
QFN-16C(2x2) · 2.00×2.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH211C (QFN-16C(2x2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH211C (QFN-16C(2x2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH211
P1 · p01_fig011599×1046px
CH211C (QFN-16C(2x2)) — 2、特点
2、特点
P2 · p02_fig011790×1009px
CH211C (QFN-16C(2x2)) — 蓝色引脚为支持高电压的引脚。 CH211C 体积小，印字为211C 及第二行的批号代码。
蓝色引脚为支持高电压的引脚。 CH211C 体积小，印字为211C 及第二行的批号代码。
P2 · p02_fig01P2
CH211C (QFN-16C(2x2)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P14 · p14_fig011301×261px
CH211C (QFN-16C(2x2)) — 6.3. 接口时序参数（测试条件：TA=25℃，VSYS=5～28V，参考附图）
6.3. 接口时序参数（测试条件：TA=25℃，VSYS=5～28V，参考附图）
P15 · p15_fig011579×1179px
CH211C (QFN-16C(2x2)) — 7.2. 一键开关与DRP
7.2. 一键开关与DRP
P15 · p15_fig021821×1212px
CH211C (QFN-16C(2x2)) — CH211 为PDUSB MCU（例如CH32X035 或CH32L103）提供Type-C 的Rd 下拉电阻，支持PD Source、 Sink 和DRP，HVCP 引脚产生高压可以控制DCDC 通断，为电池充电或者反向输出。如果仅用于Source， 那么两个CCPDG 引脚应该悬空，CH211 的VBUS 引脚无需连接。
CH211 为PDUSB MCU（例如CH32X035 或CH32L103）提供Type-C 的Rd 下拉电阻，支持PD Source、 Sink 和DRP，HVCP 引脚产生高压可以控制DCDC 通断，为电池充电或者反向输出。如果仅用于Source， 那么两个CCPDG 引脚应该悬空，CH211 的VBUS 引脚无需连接。

Technical Specifications & Part Details (CH211C)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH211C (QFN-16C(2x2)) is a 16-pin standard electronic & interconnect component featuring a 2.00 × 2.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 2.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-16C(2x2))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol17 auto-grouped pins
OK
IPC-7351B Land Pattern17 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.20×1.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-16C(2x2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.30 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-16C(2x2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH211C (QFN-16C(2x2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH211C (QFN-16C(2x2))?

Manufactured by WCH, the CH211C is housed in a QFN-16C(2x2) package with 17 pins and a 0.40 mm lead pitch. Key pins include: 1 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 2 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 3 (ODL1: Multiplexed I/O & Peripheral Pin ODL1 (General)), 4 (ODL2: Multiplexed I/O & Peripheral Pin ODL2 (General)), 5 (CCL1: Multiplexed I/O & Peripheral Pin CCL1 (General)), 6 (CCL2: Multiplexed I/O & Peripheral Pin CCL2 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH211C?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH211C (QFN-16C(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.40 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 1.20 × 1.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH211C?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH211C (WCH, QFN-16C(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (17 pins) & CH211 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
2SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
3ODL1Digital_IOSignal terminal ODL1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ODL1. Supported peripheral buses: General.
4ODL2Digital_IOSignal terminal ODL2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ODL2. Supported peripheral buses: General.
5CCL1Digital_IOSignal terminal CCL1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCL1. Supported peripheral buses: General.
6CCL2Digital_IOSignal terminal CCL2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCL2. Supported peripheral buses: General.
7HVIODigital_IOSignal terminal HVIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVIO. Supported peripheral buses: General.
8KEYDigital_IOSignal terminal KEY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: KEY. Supported peripheral buses: General.
9CCPDG2Digital_IOSignal terminal CCPDG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCPDG2. Supported peripheral buses: General.
10CCPDG1Digital_IOSignal terminal CCPDG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCPDG1. Supported peripheral buses: General.
11CCH2Digital_IOSignal terminal CCH2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCH2. Supported peripheral buses: General.
12CCH1Digital_IOSignal terminal CCH1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCH1. Supported peripheral buses: General.
13ODH2Digital_IOSignal terminal ODH2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ODH2. Supported peripheral buses: General.
14ODH1Digital_IOSignal terminal ODH1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ODH1. Supported peripheral buses: General.
15HVCPDigital_IOSignal terminal HVCP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVCP. Supported peripheral buses: General.
16VBUSPower_InPrimary positive power supply input (VBUS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
17VSYSDigital_IOSignal terminal VSYS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSYS. Supported peripheral buses: General.
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