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STM32WBA5MMGH6TR (LGA-76(8x12.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WBA5MMGH6TR

STID: C49304689LGA-76(8x12.5) · 76 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WBA5MMGH6TR (LGA-76(8x12.5))1GND2GND3GND4GND5GND6GND7PA108PA99PB1410PB1311PB1212PB1113PA814PA715PA616PA417PA318PA019GND20VDDA21GND22VDD23GND24PA125PA226PB927PA528PC1329PB830PB631PB732PB333PB534PA1535PB436GND37PA1438PA1376GND75GND74GND73GND72GND71GND70GND69GND68GND67GND66GND65GND64GND63GND62GND61GND60GND59GND58GND57GND56GND55GND54GND53GND52GND51ANT_IN50ANT_OUT49GND48NRST47GND46BOOT045GND44PB1543PB042PB141PB240PA1139PA12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.853.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3mm
2. 2D FOOTPRINT
22232425262728293031323334353676757473727170696867666564636261605958575655545352515049484746454443424140393837212019181716151413121110987654321E=8.00mm · Pitch e=0.50mmD=12.50mm-7-5-3-1135797531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 8.00mm × 12.50mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (76/76)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
2GNDGNDGround Reference Pin (GND)
3GNDGNDGround Reference Pin (GND)
4GNDGNDGround Reference Pin (GND)
5GNDGNDGround Reference Pin (GND)
6GNDGNDGround Reference Pin (GND)
7PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
8PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
9PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
10PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
11PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
12PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
13PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
14PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
15PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
16PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
18PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
19GNDGNDGround Reference Pin (GND)
20VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
21GNDGNDGround Reference Pin (GND)
22VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
23GNDGNDGround Reference Pin (GND)
24PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
25PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
26PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
27PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
28PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
29PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
30PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
31PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
32PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
33PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
34PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
35PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
36GNDGNDGround Reference Pin (GND)
37PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
38PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
39PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
40PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
41PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
42PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
43PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
44PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
45GNDGNDGround Reference Pin (GND)
46BOOT0IInput-Only Pin BOOT0 (General)
47GNDGNDGround Reference Pin (GND)
48NRSTISystem Enable & Hardware Reset (NRST)
49GNDGNDExposed Thermal & Ground Pad (GND)
50ANT_OUTI/OMultiplexed I/O & Peripheral Pin ANT_OUT (General)
51ANT_INI/OMultiplexed I/O & Peripheral Pin ANT_IN (General)
52GNDGNDGround Reference Pin (GND)
53GNDGNDGround Reference Pin (GND)
54GNDGNDGround Reference Pin (GND)
55GNDGNDGround Reference Pin (GND)
56GNDGNDGround Reference Pin (GND)
57GNDGNDExposed Thermal & Ground Pad (GND)
58GNDGNDGround Reference Pin (GND)
59GNDGNDGround Reference Pin (GND)
60GNDGNDGround Reference Pin (GND)
61GNDGNDGround Reference Pin (GND)
62GNDGNDGround Reference Pin (GND)
63GNDGNDGround Reference Pin (GND)
64GNDGNDGround Reference Pin (GND)
65GNDGNDExposed Thermal & Ground Pad (GND)
66GNDGNDGround Reference Pin (GND)
67GNDGNDGround Reference Pin (GND)
68GNDGNDGround Reference Pin (GND)
69GNDGNDGround Reference Pin (GND)
70GNDGNDGround Reference Pin (GND)
71GNDGNDGround Reference Pin (GND)
72GNDGNDGround Reference Pin (GND)
73GNDGNDGround Reference Pin (GND)
74GNDGNDGround Reference Pin (GND)
75GNDGNDGround Reference Pin (GND)
76GNDGNDGround Reference Pin (GND)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WBA5MMGH6TR (ST · LGA-76(8x12.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WBA5MMGH6TR (LGA-76(8x12.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WBA5MMGH6TR (LGA-76(8x12.5)) - 2. Standard Pinout (Top View)
True package pinout (76 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WBA5MMGH6TR (LGA-76(8x12.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WBA5MMGH6TR (LGA-76(8x12.5)) - 4. Package Dimensions (D×E×A)
LGA-76(8x12.5) · 8.00×12.50mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WBA5MMGH6TR (LGA-76(8x12.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (76 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WBA5MMGH6TR (LGA-76(8x12.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for STM32WBA5MMG
P1 · p01_fig01EXACT PACKAGE
STM32WBA5MMGH6TR (LGA-76(8x12.5)) — • Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
• Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
P12 · p12_fig01EXACT PACKAGE
STM32WBA5MMGH6TR (LGA-76(8x12.5)) — Figure 5. SiP-LGA76 - Outline SIDE VIEW bbb C M 2.961 Ref. A,
Figure 5. SiP-LGA76 - Outline SIDE VIEW bbb C M 2.961 Ref. A,
P13 · p13_fig01EXACT PACKAGE
STM32WBA5MMGH6TR (LGA-76(8x12.5)) — A1 0.030 ± 0.020 0.0012 ± 0.0008
A1 0.030 ± 0.020 0.0012 ± 0.0008
P1 · p01_fig01P1
STM32WBA5MMGH6TR (LGA-76(8x12.5)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)

Technical Specifications & Part Details (STM32WBA5MMGH6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WBA5MMGH6TR (LGA-76(8x12.5)) is a 76-pin embedded microcontroller unit (mcu) featuring a 12.50 × 8.00 × 1.15 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C to 85°C with integrated Bluetooth / BLE, JTAG / SWD interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
100 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
12.50 × 8.00 × 1.15 mm (A1=0.03 mm)
Package family: LGA (LGA-76(8x12.5))
Pin Count & Lead PitchN / e
76 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, JTAG / SWD
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol76 auto-grouped pins
OK
IPC-7351B Land Pattern76 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LGA-76(8x12.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
12.50 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
76P / 76Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LGA-76(8x12.5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WBA5MMGH6TR (LGA-76(8x12.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WBA5MMGH6TR (LGA-76(8x12.5))?

Manufactured by ST, the STM32WBA5MMGH6TR is housed in a LGA-76(8x12.5) package with 76 pins and a 0.50 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (GND: Ground Reference Pin (GND)), 3 (GND: Ground Reference Pin (GND)), 4 (GND: Ground Reference Pin (GND)), 5 (GND: Ground Reference Pin (GND)), 6 (GND: Ground Reference Pin (GND)).

What are the IPC-7351B PCB Footprint dimensions for STM32WBA5MMGH6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WBA5MMGH6TR (LGA-76(8x12.5)) has a nominal body envelope of 8.00 × 12.50 mm, pitch e = 0.50 mm, and 76 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WBA5MMGH6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WBA5MMGH6TR (ST, LGA-76(8x12.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (76 pins) & STM32WBA5MMG Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
7PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
8PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
9PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
10PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
11PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
12PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
13PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
14PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
15PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
16PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
18PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
19GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
20VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
22VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
23GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
24PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
25PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
26PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
27PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
28PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
29PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
30PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
31PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
32PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
33PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
34PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
35PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
36GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
37PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
38PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
39PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
40PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
41PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
42PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
43PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
44PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
45GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
46BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50ANT_OUTRF_50OhmSignal terminal ANT_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ANT_OUT. Supported peripheral buses: General.
51ANT_INRF_50OhmSignal terminal ANT_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: ANT_IN. Supported peripheral buses: General.
52GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
53GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
54GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
55GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
56GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
57GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
58GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
59GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
60GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
61GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
62GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
63GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
64GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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