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CH32V005D6U6 (QFN-12(2x2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V005D6U6

WCHID: C49006243QFN-12(2x2) · 13 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V005D6U6 (QFN-12(2x2))1PA1/T1C2/OPN2PA13PA24VDD5PD06VDD7PC013PC612PC511PC410PC39PC28PC1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.815.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213E=2.00mm · Pitch e=0.40mmD=2.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 2.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (13/13)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA1/T1C2/OPN0/XI/A1I/OMultiplexed I/O & Peripheral Pin PA1/T1C2/OPN0/XI/A1 (RTC/CLK)
2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (ADC)
3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (ADC)
4VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
5PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
6VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
7PC0I/OMultiplexed I/O & Peripheral Pin PC0 (PWM)
8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C)
9PC2I/OMultiplexed I/O & Peripheral Pin PC2 (UART, I2C)
10PC3I/OMultiplexed I/O & Peripheral Pin PC3 (PWM)
11PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC, RTC/CLK)
12PC5I/OMultiplexed I/O & Peripheral Pin PC5 (SPI)
13PC6I/OMultiplexed I/O & Peripheral Pin PC6 (SPI)
PIN 1 PA1/T1C2/OPN0/XI/A1
I/O
Multiplexed I/O & Peripheral Pin PA1/T1C2/OPN0/XI/A1 (RTC/CLK)
Design note: Signal terminal PA1/T1C2/OPN0/XI/A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/T1C2/OPN0/XI/A1. Supported peripheral buses: RTC/CLK.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V005D6U6 (WCH · QFN-12(2x2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V005D6U6 (QFN-12(2x2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V005D6U6 (QFN-12(2x2)) - 2. Standard Pinout (Top View)
True package pinout (13 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V005D6U6 (QFN-12(2x2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V005D6U6 (QFN-12(2x2)) - 4. Package Dimensions (D×E×A)
QFN-12(2x2) · 2.00×2.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V005D6U6 (QFN-12(2x2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (13 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V005D6U6 (QFN-12(2x2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH32V005
P10 · p10_fig011401×1408px
CH32V005D6U6 (QFN-12(2x2)) — 24 CH32V006E8R 1
24 CH32V006E8R 1
P10 · p10_fig02997×652px
CH32V005D6U6 (QFN-12(2x2)) — V2.0 8
V2.0 8
P10 · p10_fig01P10
CH32V005D6U6 (QFN-12(2x2)) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)
P13 · p13_fig011008×818px
CH32V005D6U6 (QFN-12(2x2)) — 0
0
P13 · p13_fig021261×1512px
CH32V005D6U6 (QFN-12(2x2)) — PC6/T1C1_/T1C3N_/SDA_/MOSI
PC6/T1C1_/T1C3N_/SDA_/MOSI
P13 · p13_fig031232×799px
CH32V005D6U6 (QFN-12(2x2)) — V2.0 11
V2.0 11
P13 · p13_fig02P13
CH32V005D6U6 (QFN-12(2x2)) — Datasheet Page 13 (p13_fig02)
Datasheet Page 13 (p13_fig02)
P2 · p02_fig01All Packages in PDF
CH32V005D6U6 (QFN-12(2x2)) — 型号 Code Flash RAM | 通 用 I/O | 高 级 定 时 器 | 通 用 定 时 | 器 | 精 简 定 时 | 器 | 看 门 狗 | ADC | 电容 触摸 按键 | OPA 运放 | OPA 轮询 串口 I2C SPI | 最大 工作 环境 温度 | 封装 形式 | CH32V006K8U7 62K 8K 31 1 1 1 2 8+2 8 路 1 3 路 2 1 1 105℃ QFN32 | CH32V006E8R6 62K 8K 22 1 1 1 2
型号 Code Flash RAM | 通 用 I/O | 高 级 定 时 器 | 通 用 定 时 | 器 | 精 简 定 时 | 器 | 看 门 狗 | ADC | 电容 触摸 按键 | OPA 运放 | OPA 轮询 串口 I2C SPI | 最大 工作 环境 温度 | 封装 形式 | CH32V006K8U7 62K 8K 31 1 1 1 2 8+2 8 路 1 3 路 2 1 1 105℃ QFN32 | CH32V006E8R6 62K 8K 22 1 1 1 2
P40 · p40_fig01All Packages in PDF
CH32V005D6U6 (QFN-12(2x2)) — CH32V006/V005 数据手册 https://wch.cn
CH32V006/V005 数据手册 https://wch.cn

Technical Specifications & Part Details (CH32V005D6U6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V005D6U6 (QFN-12(2x2)) is a 12-pin embedded microcontroller unit (mcu) featuring a 2.00 × 2.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
2.00 × 2.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-12(2x2))
Pin Count & Lead PitchN / e
12 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol13 auto-grouped pins
OK
IPC-7351B Land Pattern13 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.10×1.10mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH32V005 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-12(2x2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
13P / 13Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-12(2x2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V005D6U6 (QFN-12(2x2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V005D6U6 (QFN-12(2x2))?

Manufactured by WCH, the CH32V005D6U6 is housed in a QFN-12(2x2) package with 13 pins and a 0.40 mm lead pitch. Key pins include: 1 (PA1/T1C2/OPN0/XI/A1: Multiplexed I/O & Peripheral Pin PA1/T1C2/OPN0/XI/A1 (RTC/CLK)), 2 (PA1: Multiplexed I/O & Peripheral Pin PA1 (ADC)), 3 (PA2: Multiplexed I/O & Peripheral Pin PA2 (ADC)), 4 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)), 5 (PD0: Multiplexed I/O & Peripheral Pin PD0 (General)), 6 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for CH32V005D6U6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V005D6U6 (QFN-12(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.40 mm, and 13 copper pads plus a central exposed thermal pad (EPAD) of 1.10 × 1.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V005D6U6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V005D6U6 (WCH, QFN-12(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (13 pins) & CH32V005 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA1/T1C2/OPN0/XI/A1Digital_IOSignal terminal PA1/T1C2/OPN0/XI/A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/T1C2/OPN0/XI/A1. Supported peripheral buses: RTC/CLK.
2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: ADC.
3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC.
4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5PD0Digital_IOSignal terminal PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: PWM.
8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SDA, SPI_NSS_. Supported peripheral buses: SPI, I2C.
9PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SCL. Supported peripheral buses: UART, I2C.
10PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: PWM.
11PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC, RTC/CLK.
12PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_SCK. Supported peripheral buses: SPI.
13PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_MOSI. Supported peripheral buses: SPI.
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