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CH9111L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9111L

WCHID: C46061834LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9111L (LQFP-48(7x7))1XI2XO3VDD334GND5NC6UD -7UD+8NC9GND10GND11GND12NC13TXD014RXD015RTS0/ GPIO016CTS0/17DTR0/GPIO218DSR0/GPIO319DCD0/GPIO420RI0/GPIO521TNOW0/GPIO622GND23GND24VIO RESET48VDDK47GND46VIO45CFG2/GPIO13/44CFG1/GPIO12/43CFG0/GPIO11/42NC41GND40VDD539NC38VDDK37NC36GND35GND34RESET33SUSP32ACT31PWR_DET30GPIO10/MOSI29GPIO9/MISO28TX_S/SCK27RX_S/SCS26GPIO8/TX_S225GPIO7/RX_S2Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
2XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
3VDD33PowerPower Supply Input (VDD33 — 1.2V to 3.3V)
4GNDGNDGround Reference Pin (GND)
5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
6UD -I/OMultiplexed I/O & Peripheral Pin UD - (USB)
7UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9GNDGNDGround Reference Pin (GND)
10GNDGNDGround Reference Pin (GND)
11GNDGNDGround Reference Pin (GND)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
14RXD0I/ORXD0 (UART)
15RTS0/ GPIO0I/OMultiplexed I/O & Peripheral Pin RTS0/ GPIO0 (UART)
16CTS0/I/OMultiplexed I/O & Peripheral Pin CTS0/ (UART)
17DTR0/GPIO2I/OMultiplexed I/O & Peripheral Pin DTR0/GPIO2 (UART)
18DSR0/GPIO3I/OMultiplexed I/O & Peripheral Pin DSR0/GPIO3 (UART)
19DCD0/GPIO4I/OMultiplexed I/O & Peripheral Pin DCD0/GPIO4 (General)
20RI0/GPIO5I/OMultiplexed I/O & Peripheral Pin RI0/GPIO5 (General)
21TNOW0/GPIO6I/OMultiplexed I/O & Peripheral Pin TNOW0/GPIO6 (General)
22GNDGNDGround Reference Pin (GND)
23GNDGNDGround Reference Pin (GND)
24VIO RESETISystem Enable & Hardware Reset (VIO RESET)
25GPIO7/RX_S2I/OMultiplexed I/O & Peripheral Pin GPIO7/RX_S2 (General)
26GPIO8/TX_S2I/OMultiplexed I/O & Peripheral Pin GPIO8/TX_S2 (General)
27RX_S/SCSI/OMultiplexed I/O & Peripheral Pin RX_S/SCS (General)
28TX_S/SCKI/OMultiplexed I/O & Peripheral Pin TX_S/SCK (SPI)
29GPIO9/MISOI/OMultiplexed I/O & Peripheral Pin GPIO9/MISO (SPI)
30GPIO10/MOSII/OMultiplexed I/O & Peripheral Pin GPIO10/MOSI (SPI)
31PWR_DETI/OMultiplexed I/O & Peripheral Pin PWR_DET (General)
32ACTI/OMultiplexed I/O & Peripheral Pin ACT (General)
33SUSPI/OMultiplexed I/O & Peripheral Pin SUSP (General)
34RESETISystem Enable & Hardware Reset (RESET)
35GNDGNDGround Reference Pin (GND)
36GNDGNDGround Reference Pin (GND)
37NCI/OMultiplexed I/O & Peripheral Pin NC (General)
38VDDKPowerPower Supply Input (VDDK — 1.2V to 3.3V)
39NCI/OMultiplexed I/O & Peripheral Pin NC (General)
40VDD5PowerPower Supply Input (VDD5 — 1.2V to 3.3V)
41GNDGNDGround Reference Pin (GND)
42NCI/OMultiplexed I/O & Peripheral Pin NC (General)
43CFG0/GPIO11/RDNEI/OMultiplexed I/O & Peripheral Pin CFG0/GPIO11/RDNE (General)
44CFG1/GPIO12/WRNFI/OMultiplexed I/O & Peripheral Pin CFG1/GPIO12/WRNF (General)
45CFG2/GPIO13/RWSI/OMultiplexed I/O & Peripheral Pin CFG2/GPIO13/RWS (General)
46VIOI/OMultiplexed I/O & Peripheral Pin VIO (General)
47GNDGNDGround Reference Pin (GND)
48VDDKPowerPower Supply Input (VDDK — 1.2V to 3.3V)
PIN 1 XI
I/O
Multiplexed I/O & Peripheral Pin XI (RTC/CLK)
Design note: Signal terminal XI (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9111L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9111L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9111L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9111L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9111L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9111L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9111L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH9111
P9 · p09_fig01EXACT PACKAGE
CH9111L (LQFP-48(7x7)) — 7.1 LQFP48 封装
7.1 LQFP48 封装
P1 · p01_fig011512×528px
CH9111L (LQFP-48(7x7)) — 图1-1 系统框图
图1-1 系统框图
P2 · p02_fig011721×1187px
CH9111L (LQFP-48(7x7)) — CH9111 手册 https://wch.cn
CH9111 手册 https://wch.cn
P10 · p10_fig011844×1487px
CH9111L (LQFP-48(7x7)) — 图8-1 高速USB 转UART 串口+SPI 接口参考电路图 +3V3 VBUS Vin 2 C1 1uF LED1
图8-1 高速USB 转UART 串口+SPI 接口参考电路图 +3V3 VBUS Vin 2 C1 1uF LED1
P10 · p10_fig01P10
CH9111L (LQFP-48(7x7)) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)

Technical Specifications & Part Details (CH9111L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9111L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.2V to 3.3V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.2V to 3.3V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9111L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9111L (LQFP-48(7x7))?

Manufactured by WCH, the CH9111L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.2V to 3.3V. Key pins include: 1 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 2 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)), 3 (VDD33: Power Supply Input (VDD33 — 1.2V to 3.3V)), 4 (GND: Ground Reference Pin (GND)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (UD -: Multiplexed I/O & Peripheral Pin UD - (USB)).

What are the IPC-7351B PCB Footprint dimensions for CH9111L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9111L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9111L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9111L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH9111 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1XIDigital_IOSignal terminal XI (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
2XODigital_IOSignal terminal XO (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
3VDD33Power_InPrimary positive power supply input (VDD33) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5NCNCSignal terminal NC (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6UD -Digital_IOSignal terminal UD - (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: UD -. Supported peripheral buses: USB.
7UD+Digital_IOSignal terminal UD+ (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
8NCNCSignal terminal NC (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
11GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
12NCNCSignal terminal NC (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13TXD0Digital_IOSignal terminal TXD0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
14RXD0Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
15RTS0/ GPIO0Digital_IOSignal terminal RTS0/ GPIO0 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RTS0/ GPIO0. Supported peripheral buses: UART.
16CTS0/Digital_IOSignal terminal CTS0/ (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CTS0/. Supported peripheral buses: UART.
17DTR0/GPIO2Digital_IOSignal terminal DTR0/GPIO2 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DTR0/GPIO2. Supported peripheral buses: UART.
18DSR0/GPIO3Digital_IOSignal terminal DSR0/GPIO3 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DSR0/GPIO3. Supported peripheral buses: UART.
19DCD0/GPIO4Digital_IOSignal terminal DCD0/GPIO4 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: DCD0/GPIO4. Supported peripheral buses: General.
20RI0/GPIO5Digital_IOSignal terminal RI0/GPIO5 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RI0/GPIO5. Supported peripheral buses: General.
21TNOW0/GPIO6Digital_IOSignal terminal TNOW0/GPIO6 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: TNOW0/GPIO6. Supported peripheral buses: General.
22GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
24VIO RESETDigital_IOActive-low hardware reset terminal (VIO RESET): pulling this pin Low resets the processor core and peripherals.
25GPIO7/RX_S2Digital_IOSignal terminal GPIO7/RX_S2 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: GPIO7/RX_S2. Supported peripheral buses: General.
26GPIO8/TX_S2Digital_IOSignal terminal GPIO8/TX_S2 (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: GPIO8/TX_S2. Supported peripheral buses: General.
27RX_S/SCSDigital_IOSignal terminal RX_S/SCS (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: RX_S/SCS. Supported peripheral buses: General.
28TX_S/SCKDigital_IOSignal terminal TX_S/SCK (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: TX_S/SCK. Supported peripheral buses: SPI.
29GPIO9/MISODigital_IOSignal terminal GPIO9/MISO (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: GPIO9/MISO. Supported peripheral buses: SPI.
30GPIO10/MOSIDigital_IOSignal terminal GPIO10/MOSI (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: GPIO10/MOSI. Supported peripheral buses: SPI.
31PWR_DETDigital_IOSignal terminal PWR_DET (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: PWR_DET. Supported peripheral buses: General.
32ACTDigital_IOSignal terminal ACT (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General.
33SUSPDigital_IOSignal terminal SUSP (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: SUSP. Supported peripheral buses: General.
34RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
35GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
36GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
37NCNCSignal terminal NC (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
38VDDKPower_InPrimary positive power supply input (VDDK) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
39NCNCSignal terminal NC (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
40VDD5Power_InPrimary positive power supply input (VDD5) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
41GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
42NCNCSignal terminal NC (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
43CFG0/GPIO11/RDNEDigital_IOSignal terminal CFG0/GPIO11/RDNE (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CFG0/GPIO11/RDNE. Supported peripheral buses: General.
44CFG1/GPIO12/WRNFDigital_IOSignal terminal CFG1/GPIO12/WRNF (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CFG1/GPIO12/WRNF. Supported peripheral buses: General.
45CFG2/GPIO13/RWSDigital_IOSignal terminal CFG2/GPIO13/RWS (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: CFG2/GPIO13/RWS. Supported peripheral buses: General.
46VIODigital_IOSignal terminal VIO (I/O, 1.2V to 3.3V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General.
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDKPower_InPrimary positive power supply input (VDDK) operating in the 1.2V to 3.3V domain (Max rating: 3.3V).
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