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CH634W6G (QFN-64-EP(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH634W6G

WCHID: C45986779QFN-64-EP(8x8) · 65 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH634W6G (QFN-64-EP(8x8))1P3_SS_TXB2P3_SS_TXA3P3_VDD124P3_SS_RXB5P3_SS_RXA6P3_HS_DP7P3_HS_DM8NC9P4_HS_DP10P4_HS_DM11P4_SS_TXB12P4_SS_TXA13P4_VDD1214P4_SS_RXB15P4_SS_RXA16GND17VFB18GND_DCDC19VSW20VDD521VDD33/VIO3322CFG023CFG124RESET#25VBUS_DET/PWR26RSVD/HUB_CC27OVCUR1#28SPI_MOSI29OVCUR2#30SPI_MISO/SDA31IO3132PWREN3#33GANG EN#_65EP64P2_HS_DM63P2_HS_DP62NC61NC60P2_SS_RXA59P2_SS_RXB58P2_VDD1257P2_SS_TXA56P2_SS_TXB55NC54VIO3353P1_HS_DM52P1_HS_DP51P1_SS_RXA50P1_SS_RXB49SMBDAT48P1_SS_TXA47P1_SS_TXB46RESET#45SCL44SUSP43NC42P1_CC141P1_CC240P2_CC139UP_SS_TXA38UP_SS_TXB37UP_HS_DP36UP_HS_DM35AVDD3334PWREN4#Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.248.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (65/65)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P3_SS_TXBI/OMultiplexed I/O & Peripheral Pin P3_SS_TXB (General)
2P3_SS_TXAI/OMultiplexed I/O & Peripheral Pin P3_SS_TXA (General)
3P3_VDD12PowerPower Supply Input (P3_VDD12 — 3.3V / 5.0V Standard Logic)
4P3_SS_RXBI/OMultiplexed I/O & Peripheral Pin P3_SS_RXB (General)
5P3_SS_RXAI/OMultiplexed I/O & Peripheral Pin P3_SS_RXA (General)
6P3_HS_DPI/OMultiplexed I/O & Peripheral Pin P3_HS_DP (General)
7P3_HS_DMI/OMultiplexed I/O & Peripheral Pin P3_HS_DM (General)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9P4_HS_DPI/OMultiplexed I/O & Peripheral Pin P4_HS_DP (General)
10P4_HS_DMI/OMultiplexed I/O & Peripheral Pin P4_HS_DM (General)
11P4_SS_TXBI/OMultiplexed I/O & Peripheral Pin P4_SS_TXB (General)
12P4_SS_TXAI/OMultiplexed I/O & Peripheral Pin P4_SS_TXA (General)
13P4_VDD12PowerPower Supply Input (P4_VDD12 — 3.3V / 5.0V Standard Logic)
14P4_SS_RXBI/OMultiplexed I/O & Peripheral Pin P4_SS_RXB (General)
15P4_SS_RXAI/OMultiplexed I/O & Peripheral Pin P4_SS_RXA (General)
16GNDGNDGround Reference Pin (GND)
17VFBI/OMultiplexed I/O & Peripheral Pin VFB (General)
18GND_DCDCGNDGround Reference Pin (GND_DCDC)
19VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
20VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
21VDD33/VIO33PowerPower Supply Input (VDD33/VIO33 — 3.3V / 5.0V Standard Logic)
22CFG0I/OMultiplexed I/O & Peripheral Pin CFG0 (General)
23CFG1I/OMultiplexed I/O & Peripheral Pin CFG1 (General)
24RESET#ISystem Enable & Hardware Reset (RESET#)
25VBUS_DET/PWR_CCPowerPower Supply Input (VBUS_DET/PWR_CC — 3.3V / 5.0V Standard Logic)
26RSVD/HUB_CCI/OMultiplexed I/O & Peripheral Pin RSVD/HUB_CC (General)
27OVCUR1#I/OMultiplexed I/O & Peripheral Pin OVCUR1# (General)
28SPI_MOSII/OMultiplexed I/O & Peripheral Pin SPI_MOSI (SPI)
29OVCUR2#I/OMultiplexed I/O & Peripheral Pin OVCUR2# (General)
30SPI_MISO/SDAI/OMultiplexed I/O & Peripheral Pin SPI_MISO/SDA (SPI, I2C)
31IO31I/OGeneral Purpose Digital I/O Pin IO31
32PWREN3#I/OMultiplexed I/O & Peripheral Pin PWREN3# (General)
33GANG EN#_I/OMultiplexed I/O & Peripheral Pin GANG EN#_ (General)
34PWREN4#I/OMultiplexed I/O & Peripheral Pin PWREN4# (General)
35AVDD33PowerPower Supply Input (AVDD33 — 3.3V / 5.0V Standard Logic)
36UP_HS_DMI/OMultiplexed I/O & Peripheral Pin UP_HS_DM (General)
37UP_HS_DPI/OMultiplexed I/O & Peripheral Pin UP_HS_DP (General)
38UP_SS_TXBI/OMultiplexed I/O & Peripheral Pin UP_SS_TXB (General)
39UP_SS_TXAI/OMultiplexed I/O & Peripheral Pin UP_SS_TXA (General)
40P2_CC1I/OMultiplexed I/O & Peripheral Pin P2_CC1 (General)
41P1_CC2I/OMultiplexed I/O & Peripheral Pin P1_CC2 (General)
42P1_CC1I/OMultiplexed I/O & Peripheral Pin P1_CC1 (General)
43NCI/OMultiplexed I/O & Peripheral Pin NC (General)
44SUSPI/OMultiplexed I/O & Peripheral Pin SUSP (General)
45SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
46RESET#ISystem Enable & Hardware Reset (RESET#)
47P1_SS_TXBI/OMultiplexed I/O & Peripheral Pin P1_SS_TXB (General)
48P1_SS_TXAI/OMultiplexed I/O & Peripheral Pin P1_SS_TXA (General)
49SMBDATI/OMultiplexed I/O & Peripheral Pin SMBDAT (General)
50P1_SS_RXBI/OMultiplexed I/O & Peripheral Pin P1_SS_RXB (General)
51P1_SS_RXAI/OMultiplexed I/O & Peripheral Pin P1_SS_RXA (General)
52P1_HS_DPI/OMultiplexed I/O & Peripheral Pin P1_HS_DP (General)
53P1_HS_DMI/OMultiplexed I/O & Peripheral Pin P1_HS_DM (General)
54VIO33I/OMultiplexed I/O & Peripheral Pin VIO33 (General)
55NCI/OMultiplexed I/O & Peripheral Pin NC (General)
56P2_SS_TXBI/OMultiplexed I/O & Peripheral Pin P2_SS_TXB (General)
57P2_SS_TXAI/OMultiplexed I/O & Peripheral Pin P2_SS_TXA (General)
58P2_VDD12PowerPower Supply Input (P2_VDD12 — 3.3V / 5.0V Standard Logic)
59P2_SS_RXBI/OMultiplexed I/O & Peripheral Pin P2_SS_RXB (General)
60P2_SS_RXAI/OMultiplexed I/O & Peripheral Pin P2_SS_RXA (General)
61NCI/OMultiplexed I/O & Peripheral Pin NC (General)
62NCI/OMultiplexed I/O & Peripheral Pin NC (General)
63P2_HS_DPI/OMultiplexed I/O & Peripheral Pin P2_HS_DP (General)
64P2_HS_DMI/OMultiplexed I/O & Peripheral Pin P2_HS_DM (General)
65EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 P3_SS_TXB
I/O
Multiplexed I/O & Peripheral Pin P3_SS_TXB (General)
Design note: Signal terminal P3_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXB. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH634W6G (WCH · QFN-64-EP(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH634W6G (QFN-64-EP(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH634W6G (QFN-64-EP(8x8)) - 2. Standard Pinout (Top View)
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH634W6G (QFN-64-EP(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH634W6G (QFN-64-EP(8x8)) - 4. Package Dimensions (D×E×A)
QFN-64-EP(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH634W6G (QFN-64-EP(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (65 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH634W6G (QFN-64-EP(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH634
P1 · p01_fig011738×1512px
CH634W6G (QFN-64-EP(8x8)) — 图1-1 系统框图
图1-1 系统框图
P3 · p03_fig011971×2469px
CH634W6G (QFN-64-EP(8x8)) — CH634 手册1 https://wch.cn
CH634 手册1 https://wch.cn
P3 · p03_fig01P3
CH634W6G (QFN-64-EP(8x8)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011849×2509px
CH634W6G (QFN-64-EP(8x8)) — 2、CH634F、CH634W5M、CH634W6T 内部没有LDO 调压器和DC-DC 降压器，需外部同时供电3.3V 和1.2V。其它型号内置3.3V 的LDO 调压器和1.2V 的DC-DC 降压器，外部单一供电5V 或3.3V。
2、CH634F、CH634W5M、CH634W6T 内部没有LDO 调压器和DC-DC 降压器，需外部同时供电3.3V 和1.2V。其它型号内置3.3V 的LDO 调压器和1.2V 的DC-DC 降压器，外部单一供电5V 或3.3V。
P6 · p06_fig011761×2487px
CH634W6G (QFN-64-EP(8x8)) — CH634 手册1 https://wch.cn
CH634 手册1 https://wch.cn
P6 · p06_fig021787×439px
CH634W6G (QFN-64-EP(8x8)) — V2.3 6
V2.3 6
P8 · p08_fig011787×1392px
CH634W6G (QFN-64-EP(8x8)) — V2.3 8
V2.3 8
P30 · p30_fig011640×1281px
CH634W6G (QFN-64-EP(8x8)) — 图8-1 CH340X 芯片参考电路图
图8-1 CH340X 芯片参考电路图
P30 · p30_fig021757×1678px
CH634W6G (QFN-64-EP(8x8)) — V2.3 30
V2.3 30
P30 · p30_fig01P30
CH634W6G (QFN-64-EP(8x8)) — Datasheet Page 30 (p30_fig01)
Datasheet Page 30 (p30_fig01)
P27 · p27_fig01All Packages in PDF
CH634W6G (QFN-64-EP(8x8)) — 3.1 QFN56 [QFN-76(9x9)]
3.1 QFN56 [QFN-76(9x9)]

Technical Specifications & Part Details (CH634W6G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH634W6G (QFN-64-EP(8x8)) is a 64-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-64-EP(8x8))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol65 auto-grouped pins
OK
IPC-7351B Land Pattern65 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.20×6.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH634 (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-64-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
65P / 65Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-64-EP(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH634W6G (QFN-64-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH634W6G (QFN-64-EP(8x8))?

Manufactured by WCH, the CH634W6G is housed in a QFN-64-EP(8x8) package with 65 pins and a 0.40 mm lead pitch. Key pins include: 1 (P3_SS_TXB: Multiplexed I/O & Peripheral Pin P3_SS_TXB (General)), 2 (P3_SS_TXA: Multiplexed I/O & Peripheral Pin P3_SS_TXA (General)), 3 (P3_VDD12: Power Supply Input (P3_VDD12 — 3.3V / 5.0V Standard Logic)), 4 (P3_SS_RXB: Multiplexed I/O & Peripheral Pin P3_SS_RXB (General)), 5 (P3_SS_RXA: Multiplexed I/O & Peripheral Pin P3_SS_RXA (General)), 6 (P3_HS_DP: Multiplexed I/O & Peripheral Pin P3_HS_DP (General)).

What are the IPC-7351B PCB Footprint dimensions for CH634W6G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH634W6G (QFN-64-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 65 copper pads plus a central exposed thermal pad (EPAD) of 6.20 × 6.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH634W6G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH634W6G (WCH, QFN-64-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (65 pins) & CH634 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P3_SS_TXBDigital_IOSignal terminal P3_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXB. Supported peripheral buses: General.
2P3_SS_TXADigital_IOSignal terminal P3_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXA. Supported peripheral buses: General.
3P3_VDD12Power_InPrimary positive power supply input (P3_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4P3_SS_RXBDigital_IOSignal terminal P3_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXB. Supported peripheral buses: General.
5P3_SS_RXADigital_IOSignal terminal P3_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXA. Supported peripheral buses: General.
6P3_HS_DPDigital_IOSignal terminal P3_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HS_DP. Supported peripheral buses: General.
7P3_HS_DMDigital_IOSignal terminal P3_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HS_DM. Supported peripheral buses: General.
8NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9P4_HS_DPDigital_IOSignal terminal P4_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DP. Supported peripheral buses: General.
10P4_HS_DMDigital_IOSignal terminal P4_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DM. Supported peripheral buses: General.
11P4_SS_TXBDigital_IOSignal terminal P4_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXB. Supported peripheral buses: General.
12P4_SS_TXADigital_IOSignal terminal P4_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXA. Supported peripheral buses: General.
13P4_VDD12Power_InPrimary positive power supply input (P4_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14P4_SS_RXBDigital_IOSignal terminal P4_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXB. Supported peripheral buses: General.
15P4_SS_RXADigital_IOSignal terminal P4_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXA. Supported peripheral buses: General.
16GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
17VFBDigital_IOSignal terminal VFB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VFB. Supported peripheral buses: General.
18GND_DCDCGND0V electrical ground return terminal (GND_DCDC) for internal core logic, I/O drivers, and analog sub-blocks.
19VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
20VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21VDD33/VIO33Power_InPrimary positive power supply input (VDD33/VIO33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22CFG0Digital_IOSignal terminal CFG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG0. Supported peripheral buses: General.
23CFG1Digital_IOSignal terminal CFG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG1. Supported peripheral buses: General.
24RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
25VBUS_DET/PWR_CCPower_InPrimary positive power supply input (VBUS_DET/PWR_CC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26RSVD/HUB_CCDigital_IOSignal terminal RSVD/HUB_CC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD/HUB_CC. Supported peripheral buses: General.
27OVCUR1#Digital_IOSignal terminal OVCUR1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR1#. Supported peripheral buses: General.
28SPI_MOSIDigital_IOSignal terminal SPI_MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_MOSI. Supported peripheral buses: SPI.
29OVCUR2#Digital_IOSignal terminal OVCUR2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR2#. Supported peripheral buses: General.
30SPI_MISO/SDADigital_IOSignal terminal SPI_MISO/SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_MISO/SDA. Supported peripheral buses: SPI, I2C.
31IO31Digital_IOGeneral Purpose Digital I/O Pin IO31
32PWREN3#Digital_IOSignal terminal PWREN3# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN3#. Supported peripheral buses: General.
33GANG EN#_Digital_IOSignal terminal GANG EN#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GANG EN#_. Supported peripheral buses: General.
34PWREN4#Digital_IOSignal terminal PWREN4# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN4#. Supported peripheral buses: General.
35AVDD33Power_InPrimary positive power supply input (AVDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36UP_HS_DMDigital_IOSignal terminal UP_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_HS_DM. Supported peripheral buses: General.
37UP_HS_DPDigital_IOSignal terminal UP_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_HS_DP. Supported peripheral buses: General.
38UP_SS_TXBDigital_IOSignal terminal UP_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_TXB. Supported peripheral buses: General.
39UP_SS_TXADigital_IOSignal terminal UP_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_TXA. Supported peripheral buses: General.
40P2_CC1Digital_IOSignal terminal P2_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_CC1. Supported peripheral buses: General.
41P1_CC2Digital_IOSignal terminal P1_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_CC2. Supported peripheral buses: General.
42P1_CC1Digital_IOSignal terminal P1_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_CC1. Supported peripheral buses: General.
43NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
44SUSPDigital_IOSignal terminal SUSP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSP. Supported peripheral buses: General.
45SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
46RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
47P1_SS_TXBDigital_IOSignal terminal P1_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_TXB. Supported peripheral buses: General.
48P1_SS_TXADigital_IOSignal terminal P1_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_TXA. Supported peripheral buses: General.
49SMBDATDigital_IOSignal terminal SMBDAT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SMBDAT. Supported peripheral buses: General.
50P1_SS_RXBDigital_IOSignal terminal P1_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXB. Supported peripheral buses: General.
51P1_SS_RXADigital_IOSignal terminal P1_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXA. Supported peripheral buses: General.
52P1_HS_DPDigital_IOSignal terminal P1_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DP. Supported peripheral buses: General.
53P1_HS_DMDigital_IOSignal terminal P1_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DM. Supported peripheral buses: General.
54VIO33Digital_IOSignal terminal VIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO33. Supported peripheral buses: General.
55NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
56P2_SS_TXBDigital_IOSignal terminal P2_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXB. Supported peripheral buses: General.
57P2_SS_TXADigital_IOSignal terminal P2_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXA. Supported peripheral buses: General.
58P2_VDD12Power_InPrimary positive power supply input (P2_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
59P2_SS_RXBDigital_IOSignal terminal P2_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_RXB. Supported peripheral buses: General.
60P2_SS_RXADigital_IOSignal terminal P2_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_RXA. Supported peripheral buses: General.
61NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
62NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
63P2_HS_DPDigital_IOSignal terminal P2_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HS_DP. Supported peripheral buses: General.
64P2_HS_DMDigital_IOSignal terminal P2_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HS_DM. Supported peripheral buses: General.
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