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CH634X (QFN-68(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH634X

WCHID: C48985831QFN-68(8x8) · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH634X (QFN-68(8x8))1P4_SS_TXB2P4_SS_TXA3P4_VDD124P4_SS_RXB5P4_SS_RXA6P4_HS_DP7P4_HS_DM8P3_HS_DP9P3_HS_DM10P3_SS_TXB11P3_SS_TXA12P3_VDD1213P3_SS_RXB14P3_SS_RXA15P2_SS_TXB16P2_SS_TXA17P2_VDD1218P2_SS_RXB19P2_SS_RXA20P2C_SS_RXA21P2C_SS_RXB22CFG023CFG124P2C_SS_TXB25P2_HS_DP26P2_HS_DM27OVCUR1#28PWREN1#29OVCUR2#30PWREN2#31IO3132PWREN3#33GANG EN#_34PWREN4#35VDD3369GND68UP_SS_RXA67UP_SS_RXB66UP_VDD1265UP_SS_TXA64UP_SS_TXB63UP_HS_DM62NC61P1_HS_DM60P1_HS_DP59P1_SS_TXB58P1_SS_TXA57P1_VDD1256P1_SS_RXB55P1_SS_RXA54P1C_SS_RXA53P1C_SS_RXB52P1_VDD1251P1C_SS_TXA50P1C_SS_TXB49SMBDAT48XI47XO46RESET#45SCL44SUSP43DVDD1242P1_CC141P1_CC240P2_CC139P2_CC238NC37VSW36VDD5Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.250.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P4_SS_TXBI/OMultiplexed I/O & Peripheral Pin P4_SS_TXB (General)
2P4_SS_TXAI/OMultiplexed I/O & Peripheral Pin P4_SS_TXA (General)
3P4_VDD12PowerPower Supply Input (P4_VDD12 — 3.3V / 5.0V Standard Logic)
4P4_SS_RXBI/OMultiplexed I/O & Peripheral Pin P4_SS_RXB (General)
5P4_SS_RXAI/OMultiplexed I/O & Peripheral Pin P4_SS_RXA (General)
6P4_HS_DPI/OMultiplexed I/O & Peripheral Pin P4_HS_DP (General)
7P4_HS_DMI/OMultiplexed I/O & Peripheral Pin P4_HS_DM (General)
8P3_HS_DPI/OMultiplexed I/O & Peripheral Pin P3_HS_DP (General)
9P3_HS_DMI/OMultiplexed I/O & Peripheral Pin P3_HS_DM (General)
10P3_SS_TXBI/OMultiplexed I/O & Peripheral Pin P3_SS_TXB (General)
11P3_SS_TXAI/OMultiplexed I/O & Peripheral Pin P3_SS_TXA (General)
12P3_VDD12PowerPower Supply Input (P3_VDD12 — 3.3V / 5.0V Standard Logic)
13P3_SS_RXBI/OMultiplexed I/O & Peripheral Pin P3_SS_RXB (General)
14P3_SS_RXAI/OMultiplexed I/O & Peripheral Pin P3_SS_RXA (General)
15P2_SS_TXBI/OMultiplexed I/O & Peripheral Pin P2_SS_TXB (General)
16P2_SS_TXAI/OMultiplexed I/O & Peripheral Pin P2_SS_TXA (General)
17P2_VDD12PowerPower Supply Input (P2_VDD12 — 3.3V / 5.0V Standard Logic)
18P2_SS_RXBI/OMultiplexed I/O & Peripheral Pin P2_SS_RXB (General)
19P2_SS_RXAI/OMultiplexed I/O & Peripheral Pin P2_SS_RXA (General)
20P2C_SS_RXAI/OMultiplexed I/O & Peripheral Pin P2C_SS_RXA (General)
21P2C_SS_RXBI/OMultiplexed I/O & Peripheral Pin P2C_SS_RXB (General)
22CFG0I/OMultiplexed I/O & Peripheral Pin CFG0 (General)
23CFG1I/OMultiplexed I/O & Peripheral Pin CFG1 (General)
24P2C_SS_TXBI/OMultiplexed I/O & Peripheral Pin P2C_SS_TXB (General)
25P2_HS_DPI/OMultiplexed I/O & Peripheral Pin P2_HS_DP (General)
26P2_HS_DMI/OMultiplexed I/O & Peripheral Pin P2_HS_DM (General)
27OVCUR1#I/OMultiplexed I/O & Peripheral Pin OVCUR1# (General)
28PWREN1#I/OMultiplexed I/O & Peripheral Pin PWREN1# (General)
29OVCUR2#I/OMultiplexed I/O & Peripheral Pin OVCUR2# (General)
30PWREN2#I/OMultiplexed I/O & Peripheral Pin PWREN2# (General)
31IO31I/OGeneral Purpose Digital I/O Pin IO31
32PWREN3#I/OMultiplexed I/O & Peripheral Pin PWREN3# (General)
33GANG EN#_I/OMultiplexed I/O & Peripheral Pin GANG EN#_ (General)
34PWREN4#I/OMultiplexed I/O & Peripheral Pin PWREN4# (General)
35VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
36VDD5PowerPower Supply Input (VDD5 — 3.3V / 5.0V Standard Logic)
37VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
38NCI/OMultiplexed I/O & Peripheral Pin NC (General)
39P2_CC2I/OMultiplexed I/O & Peripheral Pin P2_CC2 (General)
40P2_CC1I/OMultiplexed I/O & Peripheral Pin P2_CC1 (General)
41P1_CC2I/OMultiplexed I/O & Peripheral Pin P1_CC2 (General)
42P1_CC1I/OMultiplexed I/O & Peripheral Pin P1_CC1 (General)
43DVDD12PowerPower Supply Input (DVDD12 — 3.3V / 5.0V Standard Logic)
44SUSPI/OMultiplexed I/O & Peripheral Pin SUSP (General)
45SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
46RESET#ISystem Enable & Hardware Reset (RESET#)
47XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
48XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
49SMBDATI/OMultiplexed I/O & Peripheral Pin SMBDAT (General)
50P1C_SS_TXBI/OMultiplexed I/O & Peripheral Pin P1C_SS_TXB (General)
51P1C_SS_TXAI/OMultiplexed I/O & Peripheral Pin P1C_SS_TXA (General)
52P1_VDD12PowerPower Supply Input (P1_VDD12 — 3.3V / 5.0V Standard Logic)
53P1C_SS_RXBI/OMultiplexed I/O & Peripheral Pin P1C_SS_RXB (General)
54P1C_SS_RXAI/OMultiplexed I/O & Peripheral Pin P1C_SS_RXA (General)
55P1_SS_RXAI/OMultiplexed I/O & Peripheral Pin P1_SS_RXA (General)
56P1_SS_RXBI/OMultiplexed I/O & Peripheral Pin P1_SS_RXB (General)
57P1_VDD12PowerPower Supply Input (P1_VDD12 — 3.3V / 5.0V Standard Logic)
58P1_SS_TXAI/OMultiplexed I/O & Peripheral Pin P1_SS_TXA (General)
59P1_SS_TXBI/OMultiplexed I/O & Peripheral Pin P1_SS_TXB (General)
60P1_HS_DPI/OMultiplexed I/O & Peripheral Pin P1_HS_DP (General)
61P1_HS_DMI/OMultiplexed I/O & Peripheral Pin P1_HS_DM (General)
62NCI/OMultiplexed I/O & Peripheral Pin NC (General)
63UP_HS_DMI/OMultiplexed I/O & Peripheral Pin UP_HS_DM (General)
64UP_SS_TXBI/OMultiplexed I/O & Peripheral Pin UP_SS_TXB (General)
65UP_SS_TXAI/OMultiplexed I/O & Peripheral Pin UP_SS_TXA (General)
66UP_VDD12PowerPower Supply Input (UP_VDD12 — 3.3V / 5.0V Standard Logic)
67UP_SS_RXBI/OMultiplexed I/O & Peripheral Pin UP_SS_RXB (General)
68UP_SS_RXAI/OMultiplexed I/O & Peripheral Pin UP_SS_RXA (General)
69GNDGNDGround Reference Pin (GND)
PIN 1 P4_SS_TXB
I/O
Multiplexed I/O & Peripheral Pin P4_SS_TXB (General)
Design note: Signal terminal P4_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXB. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH634X (WCH · QFN-68(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH634X (QFN-68(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH634X (QFN-68(8x8)) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH634X (QFN-68(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH634X (QFN-68(8x8)) - 4. Package Dimensions (D×E×A)
QFN-68(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH634X (QFN-68(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH634X (QFN-68(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH634
P10 · p10_fig01EXACT PACKAGE
CH634X (QFN-68(8x8)) — V2.3 10
V2.3 10
P30 · p30_fig01EXACT PACKAGE
CH634X (QFN-68(8x8)) — 图8-1 CH340X 芯片参考电路图
图8-1 CH340X 芯片参考电路图
P1 · p01_fig011738×1512px
CH634X (QFN-68(8x8)) — 图1-1 系统框图
图1-1 系统框图
P3 · p03_fig011971×2469px
CH634X (QFN-68(8x8)) — CH634 手册1 https://wch.cn
CH634 手册1 https://wch.cn
P3 · p03_fig01P3
CH634X (QFN-68(8x8)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011849×2509px
CH634X (QFN-68(8x8)) — 2、CH634F、CH634W5M、CH634W6T 内部没有LDO 调压器和DC-DC 降压器，需外部同时供电3.3V 和1.2V。其它型号内置3.3V 的LDO 调压器和1.2V 的DC-DC 降压器，外部单一供电5V 或3.3V。
2、CH634F、CH634W5M、CH634W6T 内部没有LDO 调压器和DC-DC 降压器，需外部同时供电3.3V 和1.2V。其它型号内置3.3V 的LDO 调压器和1.2V 的DC-DC 降压器，外部单一供电5V 或3.3V。
P30 · p30_fig021757×1678px
CH634X (QFN-68(8x8)) — V2.3 30
V2.3 30
P30 · p30_fig01P30
CH634X (QFN-68(8x8)) — Datasheet Page 30 (p30_fig01)
Datasheet Page 30 (p30_fig01)

Technical Specifications & Part Details (CH634X)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH634X (QFN-68(8x8)) is a 68-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-68(8x8))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 6.20×6.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-68(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-68(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH634X (QFN-68(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH634X (QFN-68(8x8))?

Manufactured by WCH, the CH634X is housed in a QFN-68(8x8) package with 69 pins and a 0.40 mm lead pitch. Key pins include: 1 (P4_SS_TXB: Multiplexed I/O & Peripheral Pin P4_SS_TXB (General)), 2 (P4_SS_TXA: Multiplexed I/O & Peripheral Pin P4_SS_TXA (General)), 3 (P4_VDD12: Power Supply Input (P4_VDD12 — 3.3V / 5.0V Standard Logic)), 4 (P4_SS_RXB: Multiplexed I/O & Peripheral Pin P4_SS_RXB (General)), 5 (P4_SS_RXA: Multiplexed I/O & Peripheral Pin P4_SS_RXA (General)), 6 (P4_HS_DP: Multiplexed I/O & Peripheral Pin P4_HS_DP (General)).

What are the IPC-7351B PCB Footprint dimensions for CH634X?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH634X (QFN-68(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 6.20 × 6.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH634X?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH634X (WCH, QFN-68(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & CH634 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P4_SS_TXBDigital_IOSignal terminal P4_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXB. Supported peripheral buses: General.
2P4_SS_TXADigital_IOSignal terminal P4_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_TXA. Supported peripheral buses: General.
3P4_VDD12Power_InPrimary positive power supply input (P4_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4P4_SS_RXBDigital_IOSignal terminal P4_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXB. Supported peripheral buses: General.
5P4_SS_RXADigital_IOSignal terminal P4_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_SS_RXA. Supported peripheral buses: General.
6P4_HS_DPDigital_IOSignal terminal P4_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DP. Supported peripheral buses: General.
7P4_HS_DMDigital_IOSignal terminal P4_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4_HS_DM. Supported peripheral buses: General.
8P3_HS_DPDigital_IOSignal terminal P3_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HS_DP. Supported peripheral buses: General.
9P3_HS_DMDigital_IOSignal terminal P3_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_HS_DM. Supported peripheral buses: General.
10P3_SS_TXBDigital_IOSignal terminal P3_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXB. Supported peripheral buses: General.
11P3_SS_TXADigital_IOSignal terminal P3_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_TXA. Supported peripheral buses: General.
12P3_VDD12Power_InPrimary positive power supply input (P3_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13P3_SS_RXBDigital_IOSignal terminal P3_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXB. Supported peripheral buses: General.
14P3_SS_RXADigital_IOSignal terminal P3_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3_SS_RXA. Supported peripheral buses: General.
15P2_SS_TXBDigital_IOSignal terminal P2_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXB. Supported peripheral buses: General.
16P2_SS_TXADigital_IOSignal terminal P2_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_TXA. Supported peripheral buses: General.
17P2_VDD12Power_InPrimary positive power supply input (P2_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18P2_SS_RXBDigital_IOSignal terminal P2_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_RXB. Supported peripheral buses: General.
19P2_SS_RXADigital_IOSignal terminal P2_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_SS_RXA. Supported peripheral buses: General.
20P2C_SS_RXADigital_IOSignal terminal P2C_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2C_SS_RXA. Supported peripheral buses: General.
21P2C_SS_RXBDigital_IOSignal terminal P2C_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2C_SS_RXB. Supported peripheral buses: General.
22CFG0Digital_IOSignal terminal CFG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG0. Supported peripheral buses: General.
23CFG1Digital_IOSignal terminal CFG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG1. Supported peripheral buses: General.
24P2C_SS_TXBDigital_IOSignal terminal P2C_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2C_SS_TXB. Supported peripheral buses: General.
25P2_HS_DPDigital_IOSignal terminal P2_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HS_DP. Supported peripheral buses: General.
26P2_HS_DMDigital_IOSignal terminal P2_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_HS_DM. Supported peripheral buses: General.
27OVCUR1#Digital_IOSignal terminal OVCUR1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR1#. Supported peripheral buses: General.
28PWREN1#Digital_IOSignal terminal PWREN1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN1#. Supported peripheral buses: General.
29OVCUR2#Digital_IOSignal terminal OVCUR2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR2#. Supported peripheral buses: General.
30PWREN2#Digital_IOSignal terminal PWREN2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN2#. Supported peripheral buses: General.
31IO31Digital_IOGeneral Purpose Digital I/O Pin IO31
32PWREN3#Digital_IOSignal terminal PWREN3# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN3#. Supported peripheral buses: General.
33GANG EN#_Digital_IOSignal terminal GANG EN#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GANG EN#_. Supported peripheral buses: General.
34PWREN4#Digital_IOSignal terminal PWREN4# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN4#. Supported peripheral buses: General.
35VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36VDD5Power_InPrimary positive power supply input (VDD5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
38NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
39P2_CC2Digital_IOSignal terminal P2_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_CC2. Supported peripheral buses: General.
40P2_CC1Digital_IOSignal terminal P2_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2_CC1. Supported peripheral buses: General.
41P1_CC2Digital_IOSignal terminal P1_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_CC2. Supported peripheral buses: General.
42P1_CC1Digital_IOSignal terminal P1_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_CC1. Supported peripheral buses: General.
43DVDD12Power_InPrimary positive power supply input (DVDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
44SUSPDigital_IOSignal terminal SUSP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SUSP. Supported peripheral buses: General.
45SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
46RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
47XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
48XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
49SMBDATDigital_IOSignal terminal SMBDAT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SMBDAT. Supported peripheral buses: General.
50P1C_SS_TXBDigital_IOSignal terminal P1C_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1C_SS_TXB. Supported peripheral buses: General.
51P1C_SS_TXADigital_IOSignal terminal P1C_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1C_SS_TXA. Supported peripheral buses: General.
52P1_VDD12Power_InPrimary positive power supply input (P1_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
53P1C_SS_RXBDigital_IOSignal terminal P1C_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1C_SS_RXB. Supported peripheral buses: General.
54P1C_SS_RXADigital_IOSignal terminal P1C_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1C_SS_RXA. Supported peripheral buses: General.
55P1_SS_RXADigital_IOSignal terminal P1_SS_RXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXA. Supported peripheral buses: General.
56P1_SS_RXBDigital_IOSignal terminal P1_SS_RXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_RXB. Supported peripheral buses: General.
57P1_VDD12Power_InPrimary positive power supply input (P1_VDD12) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
58P1_SS_TXADigital_IOSignal terminal P1_SS_TXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_TXA. Supported peripheral buses: General.
59P1_SS_TXBDigital_IOSignal terminal P1_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_SS_TXB. Supported peripheral buses: General.
60P1_HS_DPDigital_IOSignal terminal P1_HS_DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DP. Supported peripheral buses: General.
61P1_HS_DMDigital_IOSignal terminal P1_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1_HS_DM. Supported peripheral buses: General.
62NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
63UP_HS_DMDigital_IOSignal terminal UP_HS_DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_HS_DM. Supported peripheral buses: General.
64UP_SS_TXBDigital_IOSignal terminal UP_SS_TXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UP_SS_TXB. Supported peripheral buses: General.
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