ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH9121T (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9121T

WCHID: C45354919TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9121T (TSSOP-20)1TXP2TXN3VDDK4XI5XO O6LINK/RESET I7ACT8VCCIO9TXD210RXD220RXN19RXP18VCC3317GND16TNOW1/RTS15CTS14TXD113RXD112TNOW211CFGGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
2TXNI/OMultiplexed I/O & Peripheral Pin TXN (General)
3VDDKPowerPower Supply Input (VDDK — 3.3V / 5.0V Standard Logic)
4XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
5XO OI/OMultiplexed I/O & Peripheral Pin XO O (RTC/CLK)
6LINK/RESET I/O PU ,ISystem Enable & Hardware Reset (LINK/RESET I/O PU ,)
7ACTI/OMultiplexed I/O & Peripheral Pin ACT (General)
8VCCIOPowerPower Supply Input (VCCIO — 3.3V / 5.0V Standard Logic)
9TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
10RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
11CFGI/OMultiplexed I/O & Peripheral Pin CFG (General)
12TNOW2I/OMultiplexed I/O & Peripheral Pin TNOW2 (General)
13RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
14TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
15CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
16TNOW1/RTSI/OMultiplexed I/O & Peripheral Pin TNOW1/RTS (UART)
17GNDGNDGround Reference Pin (GND)
18VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
19RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
20RXNI/OMultiplexed I/O & Peripheral Pin RXN (General)
PIN 1 TXP
I/O
Multiplexed I/O & Peripheral Pin TXP (General)
Design note: Signal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9121T (WCH · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9121T (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9121T (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9121T (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9121T (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9121T (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9121T (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH9121
P1 · p01_fig011470×859px
CH9121T (TSSOP-20) — 图1-1 CH9121 应用框图 2、特点
图1-1 CH9121 应用框图 2、特点
P2 · p02_fig011400×747px
CH9121T (TSSOP-20) — 3、引脚排列
3、引脚排列
P2 · p02_fig01P2
CH9121T (TSSOP-20) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011739×1053px
CH9121T (TSSOP-20) — V2.6 3 | TNOW1 输出： 发送状态输出，用于控制串口1 的RS485 收发切换。 RTS 发送请求输出： 若是低电平，表明串口1 准备好接收数据，可以连接对 端CTS 实现硬件流控。 （该引脚默认作为TNOW1，流控功能默认关闭，可通过 上位机或串口命令码配置开启，流控功能开启后，该引 脚作为RTS 使用） 表4-2 CH9121A 引脚定义 | CH9121A | 引脚号 | 引脚 名称 类型 引脚说明 | 4 RXP I/O 10BASE-T/100BASE-
V2.6 3 | TNOW1 输出： 发送状态输出，用于控制串口1 的RS485 收发切换。 RTS 发送请求输出： 若是低电平，表明串口1 准备好接收数据，可以连接对 端CTS 实现硬件流控。 （该引脚默认作为TNOW1，流控功能默认关闭，可通过 上位机或串口命令码配置开启，流控功能开启后，该引 脚作为RTS 使用） 表4-2 CH9121A 引脚定义 | CH9121A | 引脚号 | 引脚 名称 类型 引脚说明 | 4 RXP I/O 10BASE-T/100BASE-
P12 · p12_fig011365×751px
CH9121T (TSSOP-20) — 图9-1 CH9121T 硬件参考电路 U1 TXP 1 RXD2 10 TXD2 9 VCCIO 8 ACT 7 LINK/RESET 6 XO 5 XI 4 VDDK 3 CH9121T
图9-1 CH9121T 硬件参考电路 U1 TXP 1 RXD2 10 TXD2 9 VCCIO 8 ACT 7 LINK/RESET 6 XO 5 XI 4 VDDK 3 CH9121T
P12 · p12_fig021083×711px
CH9121T (TSSOP-20) — TNOW2 12
TNOW2 12
P13 · p13_fig011648×1373px
CH9121T (TSSOP-20) — 图9-2 CH9121A 硬件参考电路 GND
图9-2 CH9121A 硬件参考电路 GND
P13 · p13_fig021443×905px
CH9121T (TSSOP-20) — CH9121A 已内置了晶体Y1 的部分振荡电容，C5 和C6 可以根据晶体参数调节。对于负载电容为 12pF 的Y1，无需C5 和C6；对于负载电容为20pF 的Y1，C5 和C6 建议各15pF。 CH9121A 已内置以太网50Ω 阻抗匹配电阻，外部不要再接49.9Ω 或50Ω 电阻，等效于电压驱 动。
CH9121A 已内置了晶体Y1 的部分振荡电容，C5 和C6 可以根据晶体参数调节。对于负载电容为 12pF 的Y1，无需C5 和C6；对于负载电容为20pF 的Y1，C5 和C6 建议各15pF。 CH9121A 已内置以太网50Ω 阻抗匹配电阻，外部不要再接49.9Ω 或50Ω 电阻，等效于电压驱 动。
P13 · p13_fig01P13
CH9121T (TSSOP-20) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)

Technical Specifications & Part Details (CH9121T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9121T (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25.001 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9121T (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9121T (TSSOP-20)?

Manufactured by WCH, the CH9121T is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (TXP: Multiplexed I/O & Peripheral Pin TXP (General)), 2 (TXN: Multiplexed I/O & Peripheral Pin TXN (General)), 3 (VDDK: Power Supply Input (VDDK — 3.3V / 5.0V Standard Logic)), 4 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 5 (XO O: Multiplexed I/O & Peripheral Pin XO O (RTC/CLK)), 6 (LINK/RESET I/O PU ,: System Enable & Hardware Reset (LINK/RESET I/O PU ,)).

What are the IPC-7351B PCB Footprint dimensions for CH9121T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9121T (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9121T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9121T (WCH, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH9121 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1TXPDigital_IOSignal terminal TXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
2TXNDigital_IOSignal terminal TXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General.
3VDDKPower_InPrimary positive power supply input (VDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
5XO ODigital_IOSignal terminal XO O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO O. Supported peripheral buses: RTC/CLK.
6LINK/RESET I/O PU ,Digital_IOActive-low hardware reset terminal (LINK/RESET I/O PU ,): pulling this pin Low resets the processor core and peripherals.
7ACTDigital_IOSignal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General.
8VCCIOPower_InPrimary positive power supply input (VCCIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
10RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
11CFGDigital_IOSignal terminal CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG. Supported peripheral buses: General.
12TNOW2Digital_IOSignal terminal TNOW2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW2. Supported peripheral buses: General.
13RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
14TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
15CTSDigital_IOSignal terminal CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
16TNOW1/RTSDigital_IOSignal terminal TNOW1/RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW1/RTS. Supported peripheral buses: UART.
17GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
18VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19RXPDigital_IOSignal terminal RXP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
20RXNDigital_IOSignal terminal RXN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload