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CH592D (QFN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH592D

WCHID: C41417128QFN-20(3x3) · 21 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH592D (QFN-20(3x3))1PA11/X32KO/T2PA10/X32KI/T3VDCID4VSW5VIO33/VDD336PB15/TCK/MIS7NC8PB13/SCK0_/T9PB12/SCS_/RX10PB11/UD+/TMR11PB10/UD-/TMR21GND20PA12/SCS/PWM19PA13/SCK0/PW18PA14/MOSI/TX17PA15/MISO/RX16VDCIA15ANT14VINTA13X32MI12X32MOGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.40mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA11/X32KO/TMR2I/OMultiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)
2PA10/X32KI/TMR1I/OMultiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)
3VDCIDI/OMultiplexed I/O & Peripheral Pin VDCID (General)
4VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
5VIO33/VDD33PowerPower Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)
6PB15/TCK/MISO_/SCLI/OMultiplexed I/O & Peripheral Pin PB15/TCK/MISO_/SCL (SPI, I2C)
7NCNCNo Connect (Leave Floating)
8PB13/SCK0_/TXD1_I/OMultiplexed I/O & Peripheral Pin PB13/SCK0_/TXD1_ (UART, SPI)
9PB12/SCS_/RXD1_I/OMultiplexed I/O & Peripheral Pin PB12/SCS_/RXD1_ (UART)
10PB11/UD+/TMR2_I/OMultiplexed I/O & Peripheral Pin PB11/UD+/TMR2_ (USB)
11PB10/UD-/TMR1_I/OMultiplexed I/O & Peripheral Pin PB10/UD-/TMR1_ (USB)
12X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
13X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
14VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
15ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
16VDCIAI/OMultiplexed I/O & Peripheral Pin VDCIA (General)
17PA15/MISO/RXD0_/AIN5I/OMultiplexed I/O & Peripheral Pin PA15/MISO/RXD0_/AIN5 (UART, SPI, ADC)
18PA14/MOSI/TXD0_/AIN4I/OMultiplexed I/O & Peripheral Pin PA14/MOSI/TXD0_/AIN4 (UART, SPI, ADC)
19PA13/SCK0/PWM5/AIN3I/OMultiplexed I/O & Peripheral Pin PA13/SCK0/PWM5/AIN3 (SPI, ADC, PWM)
20PA12/SCS/PWM4/AIN2I/OMultiplexed I/O & Peripheral Pin PA12/SCS/PWM4/AIN2 (ADC, PWM)
21GNDGNDGround Reference Pin (GND)
PIN 1 PA11/X32KO/TMR2
I/O
Multiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)
Design note: Signal terminal PA11/X32KO/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32KO/TMR2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH592D (WCH · QFN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH592D (QFN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH592D (QFN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH592D (QFN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH592D (QFN-20(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH592D (QFN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH592D (QFN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH591 / CH592
P1 · p01_fig01247×133px
CH592D (QFN-20(3x3)) — 概述
概述
P3 · p03_fig011716×1996px
CH592D (QFN-20(3x3)) — PA14/MOSI/TXD0_/AIN4 18 | PA13/SCK0/PWM5/AIN3 19 | PA15/MISO/RXD0_/AIN5 17 | 13 14 | 11 | 2 | 5 | 0 | 15 | 12 | 1 | PA12/SCS/PWM4/AIN2 20 | 4 3 | VDCIA 16 | CH592D | PB11/UD+/TMR2_ PB12/SCS_/RXD1_ | PB15/TCK/MISO_/SCL PB14/TIO/MOSI_/SDA/PWM
PA14/MOSI/TXD0_/AIN4 18 | PA13/SCK0/PWM5/AIN3 19 | PA15/MISO/RXD0_/AIN5 17 | 13 14 | 11 | 2 | 5 | 0 | 15 | 12 | 1 | PA12/SCS/PWM4/AIN2 20 | 4 3 | VDCIA 16 | CH592D | PB11/UD+/TMR2_ PB12/SCS_/RXD1_ | PB15/TCK/MISO_/SCL PB14/TIO/MOSI_/SDA/PWM
P7 · p07_fig011901×1755px
CH592D (QFN-20(3x3)) — CH592/CH591 数据手册 https://wch.cn
CH592/CH591 数据手册 https://wch.cn
P93 · p93_fig011713×1837px
CH592D (QFN-20(3x3)) — V1.8 91
V1.8 91
P120 · p120_fig011723×651px
CH592D (QFN-20(3x3)) — CH592 1.3 1.5 1.7 V CH591 1.8 2.05 2.3 V
CH592 1.3 1.5 1.7 V CH591 1.8 2.05 2.3 V
P120 · p120_fig01P120
CH592D (QFN-20(3x3)) — Datasheet Page 120 (p120_fig01)
Datasheet Page 120 (p120_fig01)

Technical Specifications & Part Details (CH592D)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH592D (QFN-20(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, SPI, I2C, ADC, PWM, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, SPI, I2C, ADC, PWM, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.70×1.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH592D (QFN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH592D (QFN-20(3x3))?

Manufactured by WCH, the CH592D is housed in a QFN-20(3x3) package with 21 pins and a 0.40 mm lead pitch. Key pins include: 1 (PA11/X32KO/TMR2: Multiplexed I/O & Peripheral Pin PA11/X32KO/TMR2 (General)), 2 (PA10/X32KI/TMR1: Multiplexed I/O & Peripheral Pin PA10/X32KI/TMR1 (General)), 3 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 5 (VIO33/VDD33: Power Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)), 6 (PB15/TCK/MISO_/SCL: Multiplexed I/O & Peripheral Pin PB15/TCK/MISO_/SCL (SPI, I2C)).

What are the IPC-7351B PCB Footprint dimensions for CH592D?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH592D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.70 × 1.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH592D?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH592D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH591 / CH592 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA11/X32KO/TMR2Digital_IOSignal terminal PA11/X32KO/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32KO/TMR2. Supported peripheral buses: General.
2PA10/X32KI/TMR1Digital_IOSignal terminal PA10/X32KI/TMR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/X32KI/TMR1. Supported peripheral buses: General.
3VDCIDDigital_IOSignal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
4VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
5VIO33/VDD33Power_InPrimary positive power supply input (VIO33/VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6PB15/TCK/MISO_/SCLDigital_IOSignal terminal PB15/TCK/MISO_/SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15/TCK/MISO_/SCL. Supported peripheral buses: SPI, I2C.
7NCNo_ConnectNo Connect (Leave Floating)
8PB13/SCK0_/TXD1_Digital_IOSignal terminal PB13/SCK0_/TXD1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13/SCK0_/TXD1_. Supported peripheral buses: UART, SPI.
9PB12/SCS_/RXD1_Digital_IOSignal terminal PB12/SCS_/RXD1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12/SCS_/RXD1_. Supported peripheral buses: UART.
10PB11/UD+/TMR2_Digital_IOSignal terminal PB11/UD+/TMR2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/UD+/TMR2_. Supported peripheral buses: USB.
11PB10/UD-/TMR1_Digital_IOSignal terminal PB10/UD-/TMR1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/UD-/TMR1_. Supported peripheral buses: USB.
12X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
13X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
14VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
16VDCIADigital_IOSignal terminal VDCIA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCIA. Supported peripheral buses: General.
17PA15/MISO/RXD0_/AIN5Digital_IOSignal terminal PA15/MISO/RXD0_/AIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15/MISO/RXD0_/AIN5. Supported peripheral buses: UART, SPI, ADC.
18PA14/MOSI/TXD0_/AIN4Digital_IOSignal terminal PA14/MOSI/TXD0_/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/MOSI/TXD0_/AIN4. Supported peripheral buses: UART, SPI, ADC.
19PA13/SCK0/PWM5/AIN3Digital_IOSignal terminal PA13/SCK0/PWM5/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13/SCK0/PWM5/AIN3. Supported peripheral buses: SPI, ADC, PWM.
20PA12/SCS/PWM4/AIN2AnalogSignal terminal PA12/SCS/PWM4/AIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/SCS/PWM4/AIN2. Supported peripheral buses: ADC, PWM.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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