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CH384P (LQFP-100(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH384P

WCHID: C33620944LQFP-100(14x14) · 100 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH384P (LQFP-100(14x14))1GPO2GND3GND4RSVD5WAKE#6RESET#7VCC338VCC339GND10VCC1811PECKP12PECKN13VCC18A14GND15GND16RREF17GND18PERP19PERN20VCC18A21PETN22PETP23GND24XO25XI26VCC3327GND28SCL29SDA30SDX31SCS32INT#33INT2#34INT1#35INT0#36XCKI#37GND38RXD039DCD040RI041DSR042CTS043RXD344DCD345RI346DSR347CTS348VCC1849GND50VCC33100CKSEL99GND098MDSEL97MGND96GND95CS0#94ALE93XRD#92XWR#91DTR390RTS389TXD388DTR287VCC3386GND85RTS284TXD283DTR182RTS181TXD180DTR079RTS078TXD077GND76CS2#75CS1#74TNOW073TNOW172VCC3371GND70VCC1869D068D167D266D365D464D563D662D761GND60CTS159DSR158RI157DCD156RXD155CTS254DSR253RI252DCD251RXD2Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.268.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=14.00mm · Pitch e=0.50mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GPOI/OMultiplexed I/O & Peripheral Pin GPO (General)
2GNDGNDGround Reference Pin (GND)
3GNDGNDGround Reference Pin (GND)
4RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
5WAKE#I/OMultiplexed I/O & Peripheral Pin WAKE# (General)
6RESET#ISystem Enable & Hardware Reset (RESET#)
7VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
8VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
9GNDGNDGround Reference Pin (GND)
10VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
11PECKPI/OMultiplexed I/O & Peripheral Pin PECKP (General)
12PECKNI/OMultiplexed I/O & Peripheral Pin PECKN (General)
13VCC18APowerPower Supply Input (VCC18A — 3.3V / 5.0V Standard Logic)
14GNDGNDGround Reference Pin (GND)
15GNDGNDGround Reference Pin (GND)
16RREFI/OMultiplexed I/O & Peripheral Pin RREF (General)
17GNDGNDGround Reference Pin (GND)
18PERPI/OMultiplexed I/O & Peripheral Pin PERP (General)
19PERNI/OMultiplexed I/O & Peripheral Pin PERN (General)
20VCC18APowerPower Supply Input (VCC18A — 3.3V / 5.0V Standard Logic)
21PETNI/OMultiplexed I/O & Peripheral Pin PETN (General)
22PETPI/OMultiplexed I/O & Peripheral Pin PETP (General)
23GNDGNDGround Reference Pin (GND)
24XOI/OXO (RTC/CLK)
25XII/OXI (RTC/CLK)
26VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
27GNDGNDGround Reference Pin (GND)
28SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
29SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
30SDXI/OMultiplexed I/O & Peripheral Pin SDX (General)
31SCSI/OMultiplexed I/O & Peripheral Pin SCS (General)
32INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
33INT2#I/OMultiplexed I/O & Peripheral Pin INT2# (General)
34INT1#I/OMultiplexed I/O & Peripheral Pin INT1# (General)
35INT0#I/OMultiplexed I/O & Peripheral Pin INT0# (General)
36XCKI#I/OMultiplexed I/O & Peripheral Pin XCKI# (General)
37GNDGNDGround Reference Pin (GND)
38RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
39DCD0I/OMultiplexed I/O & Peripheral Pin DCD0 (General)
40RI0I/OMultiplexed I/O & Peripheral Pin RI0 (General)
41DSR0I/OMultiplexed I/O & Peripheral Pin DSR0 (UART)
42CTS0I/OMultiplexed I/O & Peripheral Pin CTS0 (UART)
43RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
44DCD3I/OMultiplexed I/O & Peripheral Pin DCD3 (General)
45RI3I/OMultiplexed I/O & Peripheral Pin RI3 (General)
46DSR3I/OMultiplexed I/O & Peripheral Pin DSR3 (UART)
47CTS3I/OMultiplexed I/O & Peripheral Pin CTS3 (UART)
48VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
49GNDGNDExposed Thermal & Ground Pad (GND)
50VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
51RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
52DCD2I/OMultiplexed I/O & Peripheral Pin DCD2 (General)
53RI2I/OMultiplexed I/O & Peripheral Pin RI2 (General)
54DSR2I/OMultiplexed I/O & Peripheral Pin DSR2 (UART)
55CTS2I/OMultiplexed I/O & Peripheral Pin CTS2 (UART)
56RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
57DCD1I/OMultiplexed I/O & Peripheral Pin DCD1 (General)
58RI1I/OMultiplexed I/O & Peripheral Pin RI1 (General)
59DSR1I/OMultiplexed I/O & Peripheral Pin DSR1 (UART)
60CTS1I/OMultiplexed I/O & Peripheral Pin CTS1 (UART)
61GNDGNDGround Reference Pin (GND)
62D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
63D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
64D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
65D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
66D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
67D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
68D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
69D0I/OMultiplexed I/O & Peripheral Pin D0 (General)
70VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
71GNDGNDGround Reference Pin (GND)
72VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
73TNOW1I/OMultiplexed I/O & Peripheral Pin TNOW1 (General)
74TNOW0I/OMultiplexed I/O & Peripheral Pin TNOW0 (General)
75CS1#I/OMultiplexed I/O & Peripheral Pin CS1# (General)
76CS2#I/OMultiplexed I/O & Peripheral Pin CS2# (General)
77GNDGNDGround Reference Pin (GND)
78TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
79RTS0I/OMultiplexed I/O & Peripheral Pin RTS0 (UART)
80DTR0I/OMultiplexed I/O & Peripheral Pin DTR0 (UART)
81TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
82RTS1I/OMultiplexed I/O & Peripheral Pin RTS1 (UART)
83DTR1I/OMultiplexed I/O & Peripheral Pin DTR1 (UART)
84TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
85RTS2I/OMultiplexed I/O & Peripheral Pin RTS2 (UART)
86GNDGNDGround Reference Pin (GND)
87VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
88DTR2I/OMultiplexed I/O & Peripheral Pin DTR2 (UART)
89TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
90RTS3I/OMultiplexed I/O & Peripheral Pin RTS3 (UART)
91DTR3I/OMultiplexed I/O & Peripheral Pin DTR3 (UART)
92XWR#I/OMultiplexed I/O & Peripheral Pin XWR# (General)
93XRD#I/OMultiplexed I/O & Peripheral Pin XRD# (General)
94ALEI/OMultiplexed I/O & Peripheral Pin ALE (General)
95CS0#I/OMultiplexed I/O & Peripheral Pin CS0# (General)
96GNDGNDGround Reference Pin (GND)
97MGNDGNDGround Reference Pin (MGND)
98MDSELI/OMultiplexed I/O & Peripheral Pin MDSEL (General)
99GND0GNDGround Reference Pin (GND0)
100CKSELI/OMultiplexed I/O & Peripheral Pin CKSEL (General)
PIN 1 GPO
I/O
Multiplexed I/O & Peripheral Pin GPO (General)
Design note: 通用输出
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH384P (WCH · LQFP-100(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH384P (LQFP-100(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH384P (LQFP-100(14x14)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH384P (LQFP-100(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH384P (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH384P (LQFP-100(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH384P (LQFP-100(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH384
P1 · p01_fig011648×1149px
CH384P (LQFP-100(14x14)) — CH384 中文手册（二） １
CH384 中文手册（二） １
P1 · p01_fig021041×1041px
CH384P (LQFP-100(14x14)) — 2、封装
2、封装
P1 · p01_fig01P1
CH384P (LQFP-100(14x14)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig011732×2752px
CH384P (LQFP-100(14x14)) — CH384 中文手册（二） ２ | 3、引脚 | 3.1. 电源线 | 引脚号 引脚名称 类型 引脚说明 7,8,26,50,72,87 VCC33 电源 3.3V I/O 电源 10,48,70 VCC18 电源 1.8V 内核电源 13,20 VCC18A 电源 1.8V 传输电源 2,3,9,14,15,17,23,27, 37,49,61,71,77,86,96,99 GND 电源 公共接地端 | 97 NC. 空脚 禁止连接 | 3.2. PCIE 总线信号线 |
CH384 中文手册（二） ２ | 3、引脚 | 3.1. 电源线 | 引脚号 引脚名称 类型 引脚说明 7,8,26,50,72,87 VCC33 电源 3.3V I/O 电源 10,48,70 VCC18 电源 1.8V 内核电源 13,20 VCC18A 电源 1.8V 传输电源 2,3,9,14,15,17,23,27, 37,49,61,71,77,86,96,99 GND 电源 公共接地端 | 97 NC. 空脚 禁止连接 | 3.2. PCIE 总线信号线 |
P5 · p05_fig011957×1821px
CH384P (LQFP-100(14x14)) — CH384 属于高频电路，在设计PCB 板时请参考PCIE 总线规范，或者参考PCIE_PCB.PDF 文档。
CH384 属于高频电路，在设计PCB 板时请参考PCIE 总线规范，或者参考PCIE_PCB.PDF 文档。

Technical Specifications & Part Details (CH384P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH384P (LQFP-100(14x14)) is a 100-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-100(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH384P (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH384P (LQFP-100(14x14))?

Manufactured by WCH, the CH384P is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (GPO: Multiplexed I/O & Peripheral Pin GPO (General)), 2 (GND: Ground Reference Pin (GND)), 3 (GND: Ground Reference Pin (GND)), 4 (RSVD: Multiplexed I/O & Peripheral Pin RSVD (General)), 5 (WAKE#: Multiplexed I/O & Peripheral Pin WAKE# (General)), 6 (RESET#: System Enable & Hardware Reset (RESET#)).

What are the IPC-7351B PCB Footprint dimensions for CH384P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH384P (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH384P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH384P (WCH, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & CH384 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GPODigital_IOSignal terminal GPO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPO. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
5WAKE#Digital_IOSignal terminal WAKE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WAKE#. Supported peripheral buses: General.
6RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
7VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
8VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
11PECKPDigital_IOSignal terminal PECKP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKP. Supported peripheral buses: General.
12PECKNDigital_IOSignal terminal PECKN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKN. Supported peripheral buses: General.
13VCC18APower_InPrimary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
16RREFDigital_IOSignal terminal RREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RREF. Supported peripheral buses: General.
17GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
18PERPDigital_IOSignal terminal PERP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERP. Supported peripheral buses: General.
19PERNDigital_IOSignal terminal PERN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERN. Supported peripheral buses: General.
20VCC18APower_InPrimary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21PETNDigital_IOSignal terminal PETN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETN. Supported peripheral buses: General.
22PETPDigital_IOSignal terminal PETP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETP. Supported peripheral buses: General.
23GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
24XODigital_IO12 MHz crystal oscillator inverted output (XO); connect to crystal terminal and 22pF load capacitor to GND.
25XIDigital_IO12 MHz crystal oscillator input (XI); requires a 22pF load capacitor to GND (internally clocked on CH340C).
26VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
27GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
28SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
29SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
30SDXDigital_IOSignal terminal SDX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDX. Supported peripheral buses: General.
31SCSDigital_IOSignal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: General.
32INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
33INT2#Digital_IOSignal terminal INT2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT2#. Supported peripheral buses: General.
34INT1#Digital_IOSignal terminal INT1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT1#. Supported peripheral buses: General.
35INT0#Digital_IOSignal terminal INT0# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT0#. Supported peripheral buses: General.
36XCKI#Digital_IOSignal terminal XCKI# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XCKI#. Supported peripheral buses: General.
37GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
38RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
39DCD0Digital_IOSignal terminal DCD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0. Supported peripheral buses: General.
40RI0Digital_IOSignal terminal RI0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0. Supported peripheral buses: General.
41DSR0Digital_IOSignal terminal DSR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR0. Supported peripheral buses: UART.
42CTS0Digital_IOSignal terminal CTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0. Supported peripheral buses: UART.
43RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
44DCD3Digital_IOSignal terminal DCD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD3. Supported peripheral buses: General.
45RI3Digital_IOSignal terminal RI3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI3. Supported peripheral buses: General.
46DSR3Digital_IOSignal terminal DSR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR3. Supported peripheral buses: UART.
47CTS3Digital_IOSignal terminal CTS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS3. Supported peripheral buses: UART.
48VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
51RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
52DCD2Digital_IOSignal terminal DCD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD2. Supported peripheral buses: General.
53RI2Digital_IOSignal terminal RI2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI2. Supported peripheral buses: General.
54DSR2Digital_IOSignal terminal DSR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR2. Supported peripheral buses: UART.
55CTS2Digital_IOSignal terminal CTS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS2. Supported peripheral buses: UART.
56RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
57DCD1Digital_IOSignal terminal DCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1. Supported peripheral buses: General.
58RI1Digital_IOSignal terminal RI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1. Supported peripheral buses: General.
59DSR1Digital_IOSignal terminal DSR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1. Supported peripheral buses: UART.
60CTS1Digital_IOSignal terminal CTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1. Supported peripheral buses: UART.
61GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
62D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
63D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
64D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
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