VFQFPN-32-EP(5x5) · 33P
Synchronized Pinout (Symbol / 2D / 3D) (33/33)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| 2 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (General) |
| 3 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (General) |
| 4 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (General) |
| 5 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (General) |
| 6 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (General) |
| 7 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (General) |
| 8 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (General) |
| 9 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| 10 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (General) |
| 11 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 12 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (General) |
| 13 | VDD2 | Power | Power Supply Input (VDD2 — 3.3V VDD (Max 4.0V)) |
| 14 | RF1 | I/O | Multiplexed I/O & Peripheral Pin RF1 (General) |
| 15 | VDDRF | Power | Power Supply Input (VDDRF — 3.3V VDD (Max 4.0V)) |
| 16 | OSCOUT | I/O | Multiplexed I/O & Peripheral Pin OSCOUT (RTC/CLK) |
| 17 | OSCIN | I/O | Multiplexed I/O & Peripheral Pin OSCIN (RTC/CLK) |
| 18 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (General) |
| 19 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (General) |
| 20 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (General) |
| 21 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (General) |
| 22 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| 23 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| 24 | VDDSD | Power | Power Supply Input (VDDSD — 3.3V VDD (Max 4.0V)) |
| 25 | VLXSD | I/O | Multiplexed I/O & Peripheral Pin VLXSD (General) |
| 26 | VSS | GND | Ground Reference Pin (VSS) |
| 27 | VFBSD | I/O | Multiplexed I/O & Peripheral Pin VFBSD (General) |
| 28 | VCAP | I/O | Multiplexed I/O & Peripheral Pin VCAP (General) |
| 29 | RSTN | I/O | Multiplexed I/O & Peripheral Pin RSTN (General) |
| 30 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| 31 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| 32 | VDD1 | Power | Power Supply Input (VDD1 — 3.3V VDD (Max 4.0V)) |
| 33 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 PB3
I/OMultiplexed I/O & Peripheral Pin PB3 (General)
Design note: Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
VFQFPN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for STM32WB05
P1 · p01_fig02EXACT PACKAGE
P14 · p14_fig01EXACT PACKAGE
P19 · p19_fig02EXACT PACKAGE
P39 · p39_fig01EXACT PACKAGE
P40 · p40_fig01EXACT PACKAGE
P40 · p40_fig02EXACT PACKAGE
P1 · p01_fig011400×383px
P8 · p08_fig011489×477px
P19 · p19_fig011331×1101px
Technical Specifications & Part Details (STM32WB05KNV6TR)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32WB05KNV6TR (VFQFPN-32-EP(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, UART, SPI, I2S, JTAG / SWD, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VFQFPN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, UART, SPI, I2S, JTAG / SWD, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol33 auto-grouped pins
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32WB05 (2)
VFQFPN-32-EP(5x5) · 33P
Mechanical Dimensions & Land Pattern (VFQFPN-32-EP(5x5))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit VFQFPN-32-EP(5x5) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32WB05KNV6TR (VFQFPN-32-EP(5x5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32WB05KNV6TR (VFQFPN-32-EP(5x5))?
Manufactured by ST, the STM32WB05KNV6TR is housed in a VFQFPN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), 2 (PB2: Multiplexed I/O & Peripheral Pin PB2 (General)), 3 (PB1: Multiplexed I/O & Peripheral Pin PB1 (General)), 4 (PB0: Multiplexed I/O & Peripheral Pin PB0 (General)), 5 (PA3: Multiplexed I/O & Peripheral Pin PA3 (General)), 6 (PA2: Multiplexed I/O & Peripheral Pin PA2 (General)).
What are the IPC-7351B PCB Footprint dimensions for STM32WB05KNV6TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WB05KNV6TR (VFQFPN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WB05KNV6TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WB05KNV6TR (ST, VFQFPN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (33 pins) & STM32WB05 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |
| 2 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| 3 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General. |
| 4 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General. |
| 5 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General. |
| 6 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General. |
| 7 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General. |
| 8 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General. |
| 9 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General. |
| 10 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General. |
| 11 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 12 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General. |
| 13 | VDD2 | Power_In | Primary positive power supply input (VDD2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 14 | RF1 | RF_50Ohm | Signal terminal RF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF1. Supported peripheral buses: General. |
| 15 | VDDRF | Power_In | Primary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 16 | OSCOUT | Digital_IO | Signal terminal OSCOUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSCOUT. Supported peripheral buses: RTC/CLK. |
| 17 | OSCIN | Digital_IO | Signal terminal OSCIN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSCIN. Supported peripheral buses: RTC/CLK. |
| 18 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General. |
| 19 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General. |
| 20 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General. |
| 21 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General. |
| 22 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| 23 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General. |
| 24 | VDDSD | Power_In | Primary positive power supply input (VDDSD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | VLXSD | Digital_IO | Signal terminal VLXSD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSD. Supported peripheral buses: General. |
| 26 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 27 | VFBSD | Digital_IO | Signal terminal VFBSD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSD. Supported peripheral buses: General. |
| 28 | VCAP | Digital_IO | Signal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General. |
| 29 | RSTN | Digital_IO | Signal terminal RSTN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RSTN. Supported peripheral buses: General. |
| 30 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| 31 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| 32 | VDD1 | Power_In | Primary positive power supply input (VDD1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 33 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |