ChipDocs.org
⌘K
2284 PARTSUpload PDF
HV53011-E/KVX (TFBGA-59(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

HV53011-E/KVX

MICROCHIPID: C3304495TFBGA-59(8x8) · 59 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · HV53011-E/KVX (TFBGA-59(8x8))A1HV 5 OUTA3HV 4 OUTA5HV 3 OUTA7HV 2 OUTA9HV 1 OUTA11HV 0 OUTC1HV 6 OUTC3VPPSENSEC4LATCHDC5SSC6SHDNC7V LLC9V PPOC11FILPD3HVGNDD4LATCHCD5SDID6ReservedD7V CCE1HV 7 OUTE3HVGNDE4LATCHBE5SDOE6HVGNDE7VSSE9V PFE11V PPF3VNNSENSEF4LATCHAF5SCKL11HV 15 OUTL9HV 14 OUTL7HV 13 OUTL5HV 12 OUTL3HV 11 OUTL1HV 10 OUTJ11FILNJ9V NNOJ7HVGNDJ6HVGNDJ5HVGNDJ4HVGNDJ3HVGNDJ1HV 9 OUTH7HVGNDH6HVGNDH5HVGNDH4HVGNDH3NCG11V NNG9V NFG7HVGNDG6HVGNDG5HVGNDG4LATCHING3NCG1HV 8 OUTF7HVGNDF6HVGNDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.843.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2mm
2. 2D FOOTPRINT
A1A3A5A7A9A11C1C3C4C5C6C7C9C11D3D4D5D6D7E1E3E4E5E6E7E9E11F3F4F5F6F7G1G3G4G5G6G7G9G11H3H4H5H6H7J1J3J4J5J6J7J9J11L1L3L5L7L9L11E=8.00mm · Pitch e=0.65mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (59/59)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1HV 5 OUTI/OMultiplexed I/O & Peripheral Pin HV 5 OUT (General)
A3HV 4 OUTI/OMultiplexed I/O & Peripheral Pin HV 4 OUT (General)
A5HV 3 OUTI/OMultiplexed I/O & Peripheral Pin HV 3 OUT (General)
A7HV 2 OUTI/OMultiplexed I/O & Peripheral Pin HV 2 OUT (General)
A9HV 1 OUTI/OMultiplexed I/O & Peripheral Pin HV 1 OUT (General)
A11HV 0 OUTI/OMultiplexed I/O & Peripheral Pin HV 0 OUT (General)
C1HV 6 OUTI/OMultiplexed I/O & Peripheral Pin HV 6 OUT (General)
C3VPPSENSEI/OMultiplexed I/O & Peripheral Pin VPPSENSE (General)
C4LATCHDI/OMultiplexed I/O & Peripheral Pin LATCHD (General)
C5SSI/OMultiplexed I/O & Peripheral Pin SS (SPI)
C6SHDNI/OMultiplexed I/O & Peripheral Pin SHDN (General)
C7V LLI/OMultiplexed I/O & Peripheral Pin V LL (General)
C9V PPOI/OMultiplexed I/O & Peripheral Pin V PPO (General)
C11FILPI/OMultiplexed I/O & Peripheral Pin FILP (General)
D3HVGNDGNDGround Reference Pin (HVGND)
D4LATCHCI/OMultiplexed I/O & Peripheral Pin LATCHC (General)
D5SDII/OMultiplexed I/O & Peripheral Pin SDI (SPI)
D6ReservedI/OMultiplexed I/O & Peripheral Pin Reserved (General)
D7V CCI/OMultiplexed I/O & Peripheral Pin V CC (General)
E1HV 7 OUTI/OMultiplexed I/O & Peripheral Pin HV 7 OUT (General)
E3HVGNDGNDGround Reference Pin (HVGND)
E4LATCHBI/OMultiplexed I/O & Peripheral Pin LATCHB (General)
E5SDOI/OMultiplexed I/O & Peripheral Pin SDO (SPI)
E6HVGNDGNDGround Reference Pin (HVGND)
E7VSSGNDGround Reference Pin (VSS)
E9V PFI/OMultiplexed I/O & Peripheral Pin V PF (General)
E11V PPI/OMultiplexed I/O & Peripheral Pin V PP (General)
F3VNNSENSEI/OMultiplexed I/O & Peripheral Pin VNNSENSE (General)
F4LATCHAI/OMultiplexed I/O & Peripheral Pin LATCHA (General)
F5SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
F6HVGNDGNDGround Reference Pin (HVGND)
F7HVGNDGNDGround Reference Pin (HVGND)
G1HV 8 OUTI/OMultiplexed I/O & Peripheral Pin HV 8 OUT (General)
G3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
G4LATCHINI/OMultiplexed I/O & Peripheral Pin LATCHIN (SPI)
G5HVGNDGNDGround Reference Pin (HVGND)
G6HVGNDGNDGround Reference Pin (HVGND)
G7HVGNDGNDGround Reference Pin (HVGND)
G9V NFI/OMultiplexed I/O & Peripheral Pin V NF (General)
G11V NNI/OMultiplexed I/O & Peripheral Pin V NN (General)
H3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
H4HVGNDGNDGround Reference Pin (HVGND)
H5HVGNDGNDGround Reference Pin (HVGND)
H6HVGNDGNDGround Reference Pin (HVGND)
H7HVGNDGNDGround Reference Pin (HVGND)
J1HV 9 OUTI/OMultiplexed I/O & Peripheral Pin HV 9 OUT (General)
J3HVGNDGNDGround Reference Pin (HVGND)
J4HVGNDGNDGround Reference Pin (HVGND)
J5HVGNDGNDGround Reference Pin (HVGND)
J6HVGNDGNDGround Reference Pin (HVGND)
J7HVGNDGNDGround Reference Pin (HVGND)
J9V NNOI/OMultiplexed I/O & Peripheral Pin V NNO (General)
J11FILNI/OMultiplexed I/O & Peripheral Pin FILN (General)
L1HV 10 OUTI/OMultiplexed I/O & Peripheral Pin HV 10 OUT (General)
L3HV 11 OUTI/OMultiplexed I/O & Peripheral Pin HV 11 OUT (General)
L5HV 12 OUTI/OMultiplexed I/O & Peripheral Pin HV 12 OUT (General)
L7HV 13 OUTI/OMultiplexed I/O & Peripheral Pin HV 13 OUT (General)
L9HV 14 OUTI/OMultiplexed I/O & Peripheral Pin HV 14 OUT (General)
L11HV 15 OUTI/OMultiplexed I/O & Peripheral Pin HV 15 OUT (General)
PIN A1 HV 5 OUT
I/O
Multiplexed I/O & Peripheral Pin HV 5 OUT (General)
Design note: High -Voltage Output 5
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: HV53011-E/KVX (MICROCHIP · TFBGA-59(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
HV53011-E/KVX (TFBGA-59(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
HV53011-E/KVX (TFBGA-59(8x8)) - 2. Standard Pinout (Top View)
True package pinout (59 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
HV53011-E/KVX (TFBGA-59(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
HV53011-E/KVX (TFBGA-59(8x8)) - 4. Package Dimensions (D×E×A)
TFBGA-59(8x8) · 8.00×8.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
HV53011-E/KVX (TFBGA-59(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (59 Pads)Expand ›
6. Application SchematicSCHEMATIC
HV53011-E/KVX (TFBGA-59(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for HV53011
P1 · p01_fig01376×200px
HV53011-E/KVX (TFBGA-59(8x8)) — 16-Channel ±135V Push-Pull Driver with RTZ
16-Channel ±135V Push-Pull Driver with RTZ
P2 · p02_fig011595×1081px
HV53011-E/KVX (TFBGA-59(8x8)) — Typical Application Diagram
Typical Application Diagram
P2 · p02_fig01P2
HV53011-E/KVX (TFBGA-59(8x8)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011556×1592px
HV53011-E/KVX (TFBGA-59(8x8)) — HV53011
HV53011
P4 · p04_fig011263×1465px
HV53011-E/KVX (TFBGA-59(8x8)) — Block Diagram
Block Diagram
P23 · p23_fig01441×436px
HV53011-E/KVX (TFBGA-59(8x8)) — 59-Ball TFBGA (8x8x1.2 mm) Example
59-Ball TFBGA (8x8x1.2 mm) Example
P23 · p23_fig02441×436px
HV53011-E/KVX (TFBGA-59(8x8)) — 59-Ball TFBGA (8x8x1.2 mm) Example
59-Ball TFBGA (8x8x1.2 mm) Example
P23 · p23_fig01P23
HV53011-E/KVX (TFBGA-59(8x8)) — Datasheet Page 23 (p23_fig01)
Datasheet Page 23 (p23_fig01)

Technical Specifications & Part Details (HV53011-E/KVX)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:HV53011-E/KVX (TFBGA-59(8x8)) is a 59-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to 125°C with integrated SPI interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.20 mm (A1=0.25 mm)
Package family: BGA (TFBGA-59(8x8))
Pin Count & Lead PitchN / e
59 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol59 auto-grouped pins
OK
IPC-7351B Land Pattern59 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-59(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.65mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
59P / 59Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-59(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HV53011-E/KVX (TFBGA-59(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HV53011-E/KVX (TFBGA-59(8x8))?

Manufactured by MICROCHIP, the HV53011-E/KVX is housed in a TFBGA-59(8x8) package with 59 pins and a 0.65 mm lead pitch. Key pins include: A1 (HV 5 OUT: Multiplexed I/O & Peripheral Pin HV 5 OUT (General)), A3 (HV 4 OUT: Multiplexed I/O & Peripheral Pin HV 4 OUT (General)), A5 (HV 3 OUT: Multiplexed I/O & Peripheral Pin HV 3 OUT (General)), A7 (HV 2 OUT: Multiplexed I/O & Peripheral Pin HV 2 OUT (General)), A9 (HV 1 OUT: Multiplexed I/O & Peripheral Pin HV 1 OUT (General)), A11 (HV 0 OUT: Multiplexed I/O & Peripheral Pin HV 0 OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for HV53011-E/KVX?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV53011-E/KVX (TFBGA-59(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 59 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV53011-E/KVX?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV53011-E/KVX (MICROCHIP, TFBGA-59(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (59 pins) & HV53011 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1HV 5 OUTDigital_IOSignal terminal HV 5 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 5 OUT. Supported peripheral buses: General.
A3HV 4 OUTDigital_IOSignal terminal HV 4 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 4 OUT. Supported peripheral buses: General.
A5HV 3 OUTDigital_IOSignal terminal HV 3 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 3 OUT. Supported peripheral buses: General.
A7HV 2 OUTDigital_IOSignal terminal HV 2 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 2 OUT. Supported peripheral buses: General.
A9HV 1 OUTDigital_IOSignal terminal HV 1 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 1 OUT. Supported peripheral buses: General.
A11HV 0 OUTDigital_IOSignal terminal HV 0 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 0 OUT. Supported peripheral buses: General.
C1HV 6 OUTDigital_IOSignal terminal HV 6 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 6 OUT. Supported peripheral buses: General.
C3VPPSENSEDigital_IOSignal terminal VPPSENSE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VPPSENSE. Supported peripheral buses: General.
C4LATCHDDigital_IOSignal terminal LATCHD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LATCHD. Supported peripheral buses: General.
C5SSDigital_IOSignal terminal SS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPICHIPSELECT. Supported peripheral buses: SPI.
C6SHDNDigital_IOSignal terminal SHDN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SHDN. Supported peripheral buses: General.
C7V LLDigital_IOSignal terminal V LL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V LL. Supported peripheral buses: General.
C9V PPODigital_IOSignal terminal V PPO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V PPO. Supported peripheral buses: General.
C11FILPDigital_IOSignal terminal FILP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FILP. Supported peripheral buses: General.
D3HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
D4LATCHCDigital_IOSignal terminal LATCHC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LATCHC. Supported peripheral buses: General.
D5SDIDigital_IOSignal terminal SDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIDATAIN. Supported peripheral buses: SPI.
D6ReservedDigital_IOSignal terminal Reserved (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Reserved. Supported peripheral buses: General.
D7V CCDigital_IOSignal terminal V CC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V CC. Supported peripheral buses: General.
E1HV 7 OUTDigital_IOSignal terminal HV 7 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 7 OUT. Supported peripheral buses: General.
E3HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
E4LATCHBDigital_IOSignal terminal LATCHB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LATCHB. Supported peripheral buses: General.
E5SDODigital_IOSignal terminal SDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPIDATAOUT. Supported peripheral buses: SPI.
E6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9V PFDigital_IOSignal terminal V PF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V PF. Supported peripheral buses: General.
E11V PPDigital_IOSignal terminal V PP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V PP. Supported peripheral buses: General.
F3VNNSENSEDigital_IOSignal terminal VNNSENSE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VNNSENSE. Supported peripheral buses: General.
F4LATCHADigital_IOSignal terminal LATCHA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LATCHA. Supported peripheral buses: General.
F5SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPICLOCK. Supported peripheral buses: SPI.
F6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
F7HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
G1HV 8 OUTDigital_IOSignal terminal HV 8 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 8 OUT. Supported peripheral buses: General.
G3NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
G4LATCHINDigital_IOSignal terminal LATCHIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_DATA, SPI. Supported peripheral buses: SPI.
G5HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
G6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
G7HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
G9V NFDigital_IOSignal terminal V NF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V NF. Supported peripheral buses: General.
G11V NNDigital_IOSignal terminal V NN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V NN. Supported peripheral buses: General.
H3NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
H4HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
H5HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
H6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
H7HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
J1HV 9 OUTDigital_IOSignal terminal HV 9 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 9 OUT. Supported peripheral buses: General.
J3HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
J4HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
J5HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
J6HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
J7HVGNDGND0V electrical ground return terminal (HVGND) for internal core logic, I/O drivers, and analog sub-blocks.
J9V NNODigital_IOSignal terminal V NNO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V NNO. Supported peripheral buses: General.
J11FILNDigital_IOSignal terminal FILN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FILN. Supported peripheral buses: General.
L1HV 10 OUTDigital_IOSignal terminal HV 10 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 10 OUT. Supported peripheral buses: General.
L3HV 11 OUTDigital_IOSignal terminal HV 11 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 11 OUT. Supported peripheral buses: General.
L5HV 12 OUTDigital_IOSignal terminal HV 12 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 12 OUT. Supported peripheral buses: General.
L7HV 13 OUTDigital_IOSignal terminal HV 13 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 13 OUT. Supported peripheral buses: General.
L9HV 14 OUTDigital_IOSignal terminal HV 14 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 14 OUT. Supported peripheral buses: General.
L11HV 15 OUTDigital_IOSignal terminal HV 15 OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HV 15 OUT. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload