![CH546L (LQFP-48(7x7)) — 由Pn_MOD_OC[x]和Pn_DIR_PU[x]组合实现Pn 端口的相关配置，具体如下。](/api/v1/assets/C2923468/extracted/figures/p27_fig01.png)
![CH546L (LQFP-48(7x7)) — UART3 波特率由SBAUD3 设置产生，根据bU3SMOD 的选择分为两种情况： 当bU3SMOD=0 时，SBAUD3 = 256 - Fsys / 32 / 波特率； 当bU3SMOD=1 时，SBAUD3 = 256 - Fsys / 16 / 波特率。 UART3 中断状态寄存器(SIF3)： | 位 名称 访问 描述 复位值 | [7:2] 保留 RO 保留 000000b | 1 bU3TI RW 发送中断标志位，一个数据字节发送完后由硬件置位，需 要软件写1](/api/v1/assets/C2923468/extracted/figures/p42_fig01.png)
SOP-16 · 16P
Synchronized Pinout (Symbol / 2D / 3D) (48/48)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | 0 | I/O | Multiplexed I/O & Peripheral Pin 0 (General) |
| 2 | P1.7 | I/O | Multiplexed I/O & Peripheral Pin P1.7 (General) |
| 3 | P5.7 | I/O | Multiplexed I/O & Peripheral Pin P5.7 (General) |
| 4 | P3.0 | I/O | Multiplexed I/O & Peripheral Pin P3.0 (General) |
| 5 | P4.5 | I/O | Multiplexed I/O & Peripheral Pin P4.5 (General) |
| 6 | P4.4 | I/O | Multiplexed I/O & Peripheral Pin P4.4 (General) |
| 7 | P3.1 | I/O | Multiplexed I/O & Peripheral Pin P3.1 (General) |
| 8 | P3.2 | I/O | Multiplexed I/O & Peripheral Pin P3.2 (General) |
| 9 | P3.3 | I/O | Multiplexed I/O & Peripheral Pin P3.3 (General) |
| 10 | P3.4 | I/O | Multiplexed I/O & Peripheral Pin P3.4 (General) |
| 11 | P3.5 | I/O | Multiplexed I/O & Peripheral Pin P3.5 (General) |
| 12 | P3.6 | I/O | Multiplexed I/O & Peripheral Pin P3.6 (General) |
| 13 | P3.7 | I/O | Multiplexed I/O & Peripheral Pin P3.7 (General) |
| 14 | P4.3 | I/O | Multiplexed I/O & Peripheral Pin P4.3 (General) |
| 15 | P4.2 | I/O | Multiplexed I/O & Peripheral Pin P4.2 (General) |
| 16 | P4.6 | I/O | Multiplexed I/O & Peripheral Pin P4.6 (General) |
| 17 | XO | I/O | Multiplexed I/O & Peripheral Pin XO (RTC/CLK) |
| 18 | GND | GND | Ground Reference Pin (GND) |
| 19 | P4.1 | I/O | Multiplexed I/O & Peripheral Pin P4.1 (General) |
| 20 | P4.0 | I/O | Multiplexed I/O & Peripheral Pin P4.0 (General) |
| 21 | P2.0 | I/O | Multiplexed I/O & Peripheral Pin P2.0 (General) |
| 22 | P2.1 | I/O | Multiplexed I/O & Peripheral Pin P2.1 (General) |
| 23 | P2.2 | I/O | Multiplexed I/O & Peripheral Pin P2.2 (General) |
| 24 | P2.3 | I/O | Multiplexed I/O & Peripheral Pin P2.3 (General) |
| 25 | P2.4 | I/O | Multiplexed I/O & Peripheral Pin P2.4 (General) |
| 26 | P2.5 | I/O | Multiplexed I/O & Peripheral Pin P2.5 (General) |
| 27 | P2.6 | I/O | Multiplexed I/O & Peripheral Pin P2.6 (General) |
| 28 | P2.7 | I/O | Multiplexed I/O & Peripheral Pin P2.7 (General) |
| 29 | P5.5 | I/O | Multiplexed I/O & Peripheral Pin P5.5 (General) |
| 30 | P5.4 | I/O | Multiplexed I/O & Peripheral Pin P5.4 (General) |
| 31 | P5.1 | I/O | Multiplexed I/O & Peripheral Pin P5.1 (General) |
| 32 | P5.0 | I/O | Multiplexed I/O & Peripheral Pin P5.0 (General) |
| 33 | P0.7 | I/O | Multiplexed I/O & Peripheral Pin P0.7 (General) |
| 34 | P0.6 | I/O | Multiplexed I/O & Peripheral Pin P0.6 (General) |
| 35 | P0.5 | I/O | Multiplexed I/O & Peripheral Pin P0.5 (General) |
| 36 | P0.4 | I/O | Multiplexed I/O & Peripheral Pin P0.4 (General) |
| 37 | P0.3 | I/O | Multiplexed I/O & Peripheral Pin P0.3 (General) |
| 38 | P0.2 | I/O | Multiplexed I/O & Peripheral Pin P0.2 (General) |
| 39 | P0.1 | I/O | Multiplexed I/O & Peripheral Pin P0.1 (General) |
| 40 | P0.0 | I/O | Multiplexed I/O & Peripheral Pin P0.0 (General) |
| 41 | VDD | Power | Power Supply Input (VDD — 3.3V / 5.0V Standard Logic) |
| 42 | V33 | Power | Power Supply Input (V33 — 3.3V / 5.0V Standard Logic) |
| 43 | P1.0 | I/O | Multiplexed I/O & Peripheral Pin P1.0 (General) |
| 44 | P1.1 | I/O | Multiplexed I/O & Peripheral Pin P1.1 (General) |
| 45 | P1.2 | I/O | Multiplexed I/O & Peripheral Pin P1.2 (General) |
| 46 | P1.3 | I/O | Multiplexed I/O & Peripheral Pin P1.3 (General) |
| 47 | P1.4 | I/O | Multiplexed I/O & Peripheral Pin P1.4 (General) |
| 48 | P1.5 | I/O | Multiplexed I/O & Peripheral Pin P1.5 (General) |
PIN 1 0
I/OMultiplexed I/O & Peripheral Pin 0 (General)
Design note: 输出系统主频的4 分频时钟信号 ，即Fsys/4
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH546 / CH547
P60 · p60_fig01EXACT PACKAGE
P1 · p01_fig011717×914px
P27 · p27_fig011757×489px
P28 · p28_fig011757×1897px
P28 · p28_fig01P28
P42 · p42_fig011757×798px
P45 · p45_fig011496×347px
P45 · p45_fig021529×357px
Technical Specifications & Part Details (CH546L)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH546L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol48 auto-grouped pins
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH546 / CH547 (3)
LQFP-48(7x7) · 48P
LQFP-48(7x7) · 48P
Mechanical Dimensions & Land Pattern (LQFP-48(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-48(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH546L (LQFP-48(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH546L (LQFP-48(7x7))?
Manufactured by WCH, the CH546L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (0: Multiplexed I/O & Peripheral Pin 0 (General)), 2 (P1.7: Multiplexed I/O & Peripheral Pin P1.7 (General)), 3 (P5.7: Multiplexed I/O & Peripheral Pin P5.7 (General)), 4 (P3.0: Multiplexed I/O & Peripheral Pin P3.0 (General)), 5 (P4.5: Multiplexed I/O & Peripheral Pin P4.5 (General)), 6 (P4.4: Multiplexed I/O & Peripheral Pin P4.4 (General)).
What are the IPC-7351B PCB Footprint dimensions for CH546L?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH546L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH546L?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH546L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (48 pins) & CH546 / CH547 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | 0 | Digital_IO | Signal terminal 0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: 0. Supported peripheral buses: General. |
| 2 | P1.7 | Digital_IO | Signal terminal P1.7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.7. Supported peripheral buses: General. |
| 3 | P5.7 | Digital_IO | Signal terminal P5.7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.7. Supported peripheral buses: General. |
| 4 | P3.0 | Digital_IO | Signal terminal P3.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0. Supported peripheral buses: General. |
| 5 | P4.5 | Digital_IO | Signal terminal P4.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.5. Supported peripheral buses: General. |
| 6 | P4.4 | Digital_IO | Signal terminal P4.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.4. Supported peripheral buses: General. |
| 7 | P3.1 | Digital_IO | Signal terminal P3.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1. Supported peripheral buses: General. |
| 8 | P3.2 | Digital_IO | Signal terminal P3.2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.2. Supported peripheral buses: General. |
| 9 | P3.3 | Digital_IO | Signal terminal P3.3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3. Supported peripheral buses: General. |
| 10 | P3.4 | Digital_IO | Signal terminal P3.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4. Supported peripheral buses: General. |
| 11 | P3.5 | Digital_IO | Signal terminal P3.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.5. Supported peripheral buses: General. |
| 12 | P3.6 | Digital_IO | Signal terminal P3.6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.6. Supported peripheral buses: General. |
| 13 | P3.7 | Digital_IO | Signal terminal P3.7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.7. Supported peripheral buses: General. |
| 14 | P4.3 | Digital_IO | Signal terminal P4.3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.3. Supported peripheral buses: General. |
| 15 | P4.2 | Digital_IO | Signal terminal P4.2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.2. Supported peripheral buses: General. |
| 16 | P4.6 | Digital_IO | Signal terminal P4.6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.6. Supported peripheral buses: General. |
| 17 | XO | Digital_IO | Signal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK. |
| 18 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 19 | P4.1 | Digital_IO | Signal terminal P4.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.1. Supported peripheral buses: General. |
| 20 | P4.0 | Digital_IO | Signal terminal P4.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.0. Supported peripheral buses: General. |
| 21 | P2.0 | Digital_IO | Signal terminal P2.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.0. Supported peripheral buses: General. |
| 22 | P2.1 | Digital_IO | Signal terminal P2.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.1. Supported peripheral buses: General. |
| 23 | P2.2 | Digital_IO | Signal terminal P2.2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.2. Supported peripheral buses: General. |
| 24 | P2.3 | Digital_IO | Signal terminal P2.3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.3. Supported peripheral buses: General. |
| 25 | P2.4 | Digital_IO | Signal terminal P2.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.4. Supported peripheral buses: General. |
| 26 | P2.5 | Digital_IO | Signal terminal P2.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.5. Supported peripheral buses: General. |
| 27 | P2.6 | Digital_IO | Signal terminal P2.6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.6. Supported peripheral buses: General. |
| 28 | P2.7 | Digital_IO | Signal terminal P2.7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.7. Supported peripheral buses: General. |
| 29 | P5.5 | Digital_IO | Signal terminal P5.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.5. Supported peripheral buses: General. |
| 30 | P5.4 | Digital_IO | Signal terminal P5.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.4. Supported peripheral buses: General. |
| 31 | P5.1 | Digital_IO | Signal terminal P5.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.1. Supported peripheral buses: General. |
| 32 | P5.0 | Digital_IO | Signal terminal P5.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.0. Supported peripheral buses: General. |
| 33 | P0.7 | Digital_IO | Signal terminal P0.7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.7. Supported peripheral buses: General. |
| 34 | P0.6 | Digital_IO | Signal terminal P0.6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.6. Supported peripheral buses: General. |
| 35 | P0.5 | Digital_IO | Signal terminal P0.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.5. Supported peripheral buses: General. |
| 36 | P0.4 | Digital_IO | Signal terminal P0.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.4. Supported peripheral buses: General. |
| 37 | P0.3 | Digital_IO | Signal terminal P0.3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.3. Supported peripheral buses: General. |
| 38 | P0.2 | Digital_IO | Signal terminal P0.2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.2. Supported peripheral buses: General. |
| 39 | P0.1 | Digital_IO | Signal terminal P0.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.1. Supported peripheral buses: General. |
| 40 | P0.0 | Digital_IO | Signal terminal P0.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.0. Supported peripheral buses: General. |
| 41 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 42 | V33 | Power_In | Primary positive power supply input (V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 43 | P1.0 | Digital_IO | Signal terminal P1.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.0. Supported peripheral buses: General. |
| 44 | P1.1 | Digital_IO | Signal terminal P1.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.1. Supported peripheral buses: General. |
| 45 | P1.2 | Digital_IO | Signal terminal P1.2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.2. Supported peripheral buses: General. |
| 46 | P1.3 | Digital_IO | Signal terminal P1.3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.3. Supported peripheral buses: General. |
| 47 | P1.4 | Digital_IO | Signal terminal P1.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.4. Supported peripheral buses: General. |
| 48 | P1.5 | Digital_IO | Signal terminal P1.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.5. Supported peripheral buses: General. |