Mechanical Dimensions & Land Pattern (QFN-24-EP(4x4))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-24-EP(4x4) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH9102F (QFN-24-EP(4x4))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH9102F (QFN-24-EP(4x4))?
Manufactured by WCH, the CH9102F is housed in a QFN-24-EP(4x4) package with 25 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (RI: Multiplexed I/O & Peripheral Pin RI (UART)), 2 (GND: Ground Reference Pin (GND)), 3 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 4 (UD-: Multiplexed I/O & Peripheral Pin UD- (USB)), 5 (VIO: Multiplexed I/O & Peripheral Pin VIO (General)), 6 (V3: Regulated Power Output (V3 — 3.3V to 5V)).
What are the IPC-7351B PCB Footprint dimensions for CH9102F?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9102F (QFN-24-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.50 × 2.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9102F?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9102F (WCH, QFN-24-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (25 pins) & CH9102 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | RI | Digital_IO | Signal terminal RI (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RI. Supported peripheral buses: UART. |
| 2 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | UD+ | Digital_IO | Signal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB. |
| 4 | UD- | Digital_IO | Signal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB. |
| 5 | VIO | Digital_IO | Signal terminal VIO (I/O, 3.3V to 5V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General. |
| 6 | V3 | Power_Out | Regulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 7 | VDD5 | Power_In | Primary positive power supply input (VDD5) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 8 | VBUS | Power_In | Primary positive power supply input (VBUS) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 9 | RST# | Digital_IO | Signal terminal RST# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General. |
| 10 | ACT# | Digital_IO | Signal terminal ACT# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: ACT#. Supported peripheral buses: General. |
| 11 | WAKEUP/GPIO3 | Digital_IO | Signal terminal WAKEUP/GPIO3 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General. |
| 12 | TNOW/GPIO2 | Digital_IO | Signal terminal TNOW/GPIO2 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General. |
| 13 | RXS/GPIO1 | Digital_IO | Signal terminal RXS/GPIO1 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General. |
| 14 | TXS/GPIO0 | Digital_IO | Signal terminal TXS/GPIO0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General. |
| 15 | SUSPEND# | Digital_IO | Signal terminal SUSPEND# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: SUSPEND#. Supported peripheral buses: USB. |
| 16 | GPIO4 | Digital_IO | Signal terminal GPIO4 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General. |
| 17 | SUSPEND | Digital_IO | Signal terminal SUSPEND (I/O, 3.3V to 5V domain). Multiplexed alternate functions: SUSPEND. Supported peripheral buses: General. |
| 18 | CTS | Digital_IO | Signal terminal CTS (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART. |
| 19 | RTS | Digital_IO | Signal terminal RTS (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART. |
| 20 | RXD | Digital_IO | Signal terminal RXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART. |
| 21 | TXD | Digital_IO | Signal terminal TXD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART. |
| 22 | DSR | Digital_IO | Signal terminal DSR (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DSR. Supported peripheral buses: UART. |
| 23 | DTR | Digital_IO | Signal terminal DTR (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DTR. Supported peripheral buses: UART. |
| 24 | DCD | Digital_IO | Signal terminal DCD (I/O, 3.3V to 5V domain). Multiplexed alternate functions: DCD. Supported peripheral buses: UART. |
| 25 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |