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CH571F (QFN-28-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH571F

WCHID: C2856288QFN-28-EP(4x4) · 29 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH571F (QFN-28-EP(4x4))1PA11/X32K0/T2PA10/X32KI/T3VDCID4VSW5VDD336PA87RB_PINUSBIE_8RB PIN_ADC899RB_PINADC0IE10RB_PINADC1IE11RB_PINADC12I12RB_PINADC13I13RB_PINXT32KI14RB PIN_ADC2315RB PIN_ADC4529EP28PA12/SCS/PWM27PA13/SCK0/PW26PA14/MOST/TX25PA15/MIS0/RX24PA5/TXD3/AIN23PA4/RXD3/AIN22VICIA21ANT20VINTA19X32MI18X32M017PB22/TMR3/RX16IO18Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA11/X32K0/TMR2I/OMultiplexed I/O & Peripheral Pin PA11/X32K0/TMR2 (General)
2PA10/X32KI/TMRII/OMultiplexed I/O & Peripheral Pin PA10/X32KI/TMRI (General)
3VDCIDI/OMultiplexed I/O & Peripheral Pin VDCID (General)
4VSWI/OMultiplexed I/O & Peripheral Pin VSW (CAN)
5VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
6PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, ADC)
7RB_PINUSBIE__I/OMultiplexed I/O & Peripheral Pin RB_PINUSBIE__ (USB)
8RB PIN_ADC89IE___I/OMultiplexed I/O & Peripheral Pin RB PIN_ADC89IE___ (ADC)
9RB_PINADC0IE__I/OMultiplexed I/O & Peripheral Pin RB_PINADC0IE__ (ADC)
10RB_PINADC1IE__I/OMultiplexed I/O & Peripheral Pin RB_PINADC1IE__ (ADC)
11RB_PINADC12IE__I/OMultiplexed I/O & Peripheral Pin RB_PINADC12IE__ (ADC)
12RB_PINADC13IE__I/OMultiplexed I/O & Peripheral Pin RB_PINADC13IE__ (ADC)
13RB_PINXT32KIE__I/OMultiplexed I/O & Peripheral Pin RB_PINXT32KIE__ (General)
14RB PIN_ADC23IE___I/OMultiplexed I/O & Peripheral Pin RB PIN_ADC23IE___ (ADC)
15RB PIN_ADC45IE___I/OMultiplexed I/O & Peripheral Pin RB PIN_ADC45IE___ (ADC)
16IO18I/OGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17PB22/TMR3/RXD2I/OMultiplexed I/O & Peripheral Pin PB22/TMR3/RXD2 (UART)
18X32M0I/OMultiplexed I/O & Peripheral Pin X32M0 (General)
19X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
20VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
21ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
22VICIAI/OMultiplexed I/O & Peripheral Pin VICIA (General)
23PA4/RXD3/AINOI/OMultiplexed I/O & Peripheral Pin PA4/RXD3/AINO (UART)
24PA5/TXD3/AIN1I/OMultiplexed I/O & Peripheral Pin PA5/TXD3/AIN1 (UART, ADC)
25PA15/MIS0/RXD0/AIN5I/OMultiplexed I/O & Peripheral Pin PA15/MIS0/RXD0/AIN5 (UART, ADC)
26PA14/MOST/TXD0/AIMI/OMultiplexed I/O & Peripheral Pin PA14/MOST/TXD0/AIM (UART)
27PA13/SCK0/PWM5/AIN3I/OMultiplexed I/O & Peripheral Pin PA13/SCK0/PWM5/AIN3 (SPI, ADC, PWM)
28PA12/SCS/PWM4/AIN2I/OMultiplexed I/O & Peripheral Pin PA12/SCS/PWM4/AIN2 (ADC, PWM)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PA11/X32K0/TMR2
I/O
Multiplexed I/O & Peripheral Pin PA11/X32K0/TMR2 (General)
Design note: Signal terminal PA11/X32K0/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32K0/TMR2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH571F (WCH · QFN-28-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH571F (QFN-28-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH571F (QFN-28-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH571F (QFN-28-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH571F (QFN-28-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(4x4) · 4.00×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH571F (QFN-28-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH571F (QFN-28-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH571 / CH573
P117 · p117_fig01EXACT PACKAGE
CH571F (QFN-28-EP(4x4)) — QFN28_4X4 4.0+0.1 0.2+0. 05 LJ Ld Ld Ld Ld Ld Ld U U u y UJ u u 3) i #14[(D CT =| Jc > a = | |coq 3 > 2.840. 1 a 2 | Top View loo + > a _| P | -lo Bottom View | jt t = C | =| je => CC #2800 \ | L428 n6- = e-— — — — Fl riri ri Fi Fi rd a a a
QFN28_4X4 4.0+0.1 0.2+0. 05 LJ Ld Ld Ld Ld Ld Ld U U u y UJ u u 3) i #14[(D CT =| Jc > a = | |coq 3 > 2.840. 1 a 2 | Top View loo + > a _| P | -lo Bottom View | jt t = C | =| je => CC #2800 \ | L428 n6- = e-— — — — Fl riri ri Fi Fi rd a a a
P117 · p117_fig02EXACT PACKAGE
CH571F (QFN-28-EP(4x4)) — QFN28_4X4
QFN28_4X4
P1 · p01_fig01288×164px
CH571F (QFN-28-EP(4x4)) — V1.12 Overview
V1.12 Overview
P3 · p03_fig011696×2615px
CH571F (QFN-28-EP(4x4)) — Figure 1-1 Pinouts of CH573X, CH573F/CH571F, CH571D, CH571K and CH573Q
Figure 1-1 Pinouts of CH573X, CH573F/CH571F, CH571D, CH571K and CH573Q
P3 · p03_fig01P3
CH571F (QFN-28-EP(4x4)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P45 · p45_fig011786×346px
CH571F (QFN-28-EP(4x4)) — Table 7-5 USB USB signal pin Functional configuration GPIO configuration
Table 7-5 USB USB signal pin Functional configuration GPIO configuration
P118 · p118_fig01All Packages in PDF
CH571F (QFN-28-EP(4x4)) — LQFP32
LQFP32
P118 · p118_fig02All Packages in PDF
CH571F (QFN-28-EP(4x4)) — LQFP32
LQFP32
P93 · p93_fig011344×1019px
CH571F (QFN-28-EP(4x4)) — PACKAGE_DIMENSIONS — CH571R (TSSOP-16)
PACKAGE_DIMENSIONS — CH571R (TSSOP-16)

Technical Specifications & Part Details (CH571F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH571F (QFN-28-EP(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, ADC, PWM, CAN interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, ADC, PWM, CAN
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH571 / CH573 (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-28-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH571F (QFN-28-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH571F (QFN-28-EP(4x4))?

Manufactured by WCH, the CH571F is housed in a QFN-28-EP(4x4) package with 29 pins and a 0.40 mm lead pitch. Key pins include: 1 (PA11/X32K0/TMR2: Multiplexed I/O & Peripheral Pin PA11/X32K0/TMR2 (General)), 2 (PA10/X32KI/TMRI: Multiplexed I/O & Peripheral Pin PA10/X32KI/TMRI (General)), 3 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (CAN)), 5 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 6 (PA8: Multiplexed I/O & Peripheral Pin PA8 (UART, ADC)).

What are the IPC-7351B PCB Footprint dimensions for CH571F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH571F (QFN-28-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.40 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH571F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH571F (WCH, QFN-28-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH571 / CH573 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA11/X32K0/TMR2Digital_IOSignal terminal PA11/X32K0/TMR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11/X32K0/TMR2. Supported peripheral buses: General.
2PA10/X32KI/TMRIDigital_IOSignal terminal PA10/X32KI/TMRI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10/X32KI/TMRI. Supported peripheral buses: General.
3VDCIDDigital_IOSignal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General.
4VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: CAN.
5VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, ADC.
7RB_PINUSBIE__Digital_IOSignal terminal RB_PINUSBIE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB_PINUSBIE__. Supported peripheral buses: USB.
8RB PIN_ADC89IE___AnalogSignal terminal RB PIN_ADC89IE___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB PIN_ADC89IE___. Supported peripheral buses: ADC.
9RB_PINADC0IE__AnalogSignal terminal RB_PINADC0IE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB_PINADC0IE__. Supported peripheral buses: ADC.
10RB_PINADC1IE__AnalogSignal terminal RB_PINADC1IE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB_PINADC1IE__. Supported peripheral buses: ADC.
11RB_PINADC12IE__AnalogSignal terminal RB_PINADC12IE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB_PINADC12IE__. Supported peripheral buses: ADC.
12RB_PINADC13IE__AnalogSignal terminal RB_PINADC13IE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB_PINADC13IE__. Supported peripheral buses: ADC.
13RB_PINXT32KIE__Digital_IOSignal terminal RB_PINXT32KIE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB_PINXT32KIE__. Supported peripheral buses: General.
14RB PIN_ADC23IE___AnalogSignal terminal RB PIN_ADC23IE___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB PIN_ADC23IE___. Supported peripheral buses: ADC.
15RB PIN_ADC45IE___AnalogSignal terminal RB PIN_ADC45IE___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB PIN_ADC45IE___. Supported peripheral buses: ADC.
16IO18Digital_IOGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17PB22/TMR3/RXD2Digital_IOSignal terminal PB22/TMR3/RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22/TMR3/RXD2. Supported peripheral buses: UART.
18X32M0Digital_IOSignal terminal X32M0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32M0. Supported peripheral buses: General.
19X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
20VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
22VICIADigital_IOSignal terminal VICIA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VICIA. Supported peripheral buses: General.
23PA4/RXD3/AINODigital_IOSignal terminal PA4/RXD3/AINO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4/RXD3/AINO. Supported peripheral buses: UART.
24PA5/TXD3/AIN1Digital_IOSignal terminal PA5/TXD3/AIN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/TXD3/AIN1. Supported peripheral buses: UART, ADC.
25PA15/MIS0/RXD0/AIN5Digital_IOSignal terminal PA15/MIS0/RXD0/AIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15/MIS0/RXD0/AIN5. Supported peripheral buses: UART, ADC.
26PA14/MOST/TXD0/AIMDigital_IOSignal terminal PA14/MOST/TXD0/AIM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14/MOST/TXD0/AIM. Supported peripheral buses: UART.
27PA13/SCK0/PWM5/AIN3Digital_IOSignal terminal PA13/SCK0/PWM5/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, ADC, PWM.
28PA12/SCS/PWM4/AIN2AnalogSignal terminal PA12/SCS/PWM4/AIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12/SCS/PWM4/AIN2. Supported peripheral buses: ADC, PWM.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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