![CH342K (ESSOP-10-150mil) — Package Width of Plastic Pitch of Pin Instruction of Package Ordering Information [QFN-24-EP(4x4)]](/api/v1/assets/C2841530/extracted/pinout_diagram.png)
ESSOP-10-150mil · 11P
Synchronized Pinout (Symbol / 2D / 3D) (11/11)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | UD+ | I/O | Multiplexed I/O & Peripheral Pin UD+ (USB) |
| 2 | UD- | I/O | Multiplexed I/O & Peripheral Pin UD- (USB) |
| 3 | GND | GND | Ground Reference Pin (GND) |
| 4 | VDD5 | Power | Power Supply Input (VDD5 — 3.3V to 5V) |
| 5 | TXD1 | I/O | Multiplexed I/O & Peripheral Pin TXD1 (UART) |
| 6 | RXD1 | I/O | Multiplexed I/O & Peripheral Pin RXD1 (UART) |
| 7 | VIO | I/O | Multiplexed I/O & Peripheral Pin VIO (General) |
| 8 | TXD0 | I/O | Multiplexed I/O & Peripheral Pin TXD0 (UART) |
| 9 | RXD0 | I/O | Multiplexed I/O & Peripheral Pin RXD0 (UART) |
| 10 | V3 | Power | Regulated Power Output (V3 — 3.3V to 5V) |
| 11 | GND | GND | Ground Reference Pin (GND) |
PIN 1 UD+
I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
Design note: Signal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (11 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESSOP-10-150mil · 3.90×4.90mm · Pitch 1.00mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (11 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH342
P1 · p01_fig02EXACT PACKAGE
P1 · p01_fig011680×557px
P1 · p01_fig02P1
P5 · p05_fig011706×1764px
P6 · p06_fig011725×1314px
P6 · p06_fig01P6
P7 · p07_fig01809×986px
P7 · p07_fig02899×663px
P7 · p07_fig031095×261px
P2 · p02_fig01EXACT PACKAGE
Technical Specifications & Part Details (CH342K)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH342K (ESSOP-10-150mil) is a 10-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.10 mm mechanical envelope (lead pitch e = 1.00 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.10 mm (A1=0.05 mm)
Package family: TSSOP (ESSOP-10-150mil)
Pin Count & Lead PitchN / e
10 Pins | Pitch e = 1.00 mm (39.4 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol11 auto-grouped pins
IPC-7351B Land Pattern11 pads · Pitch 1.00mm
IPC-7525 60% Solder PasteEPAD 2.30×3.00mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH342 (2)
QFN-24-EP(4x4) · 25P
Mechanical Dimensions & Land Pattern (ESSOP-10-150mil)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=1.00mm
Pad Size (W × L)Level B
0.45 × 1.50 mm
Pins / Total PadsTopology
11P / 11Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit ESSOP-10-150mil | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH342K (ESSOP-10-150mil)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH342K (ESSOP-10-150mil)?
Manufactured by WCH, the CH342K is housed in a ESSOP-10-150mil package with 11 pins and a 1.00 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 2 (UD-: Multiplexed I/O & Peripheral Pin UD- (USB)), 3 (GND: Ground Reference Pin (GND)), 4 (VDD5: Power Supply Input (VDD5 — 3.3V to 5V)), 5 (TXD1: Multiplexed I/O & Peripheral Pin TXD1 (UART)), 6 (RXD1: Multiplexed I/O & Peripheral Pin RXD1 (UART)).
What are the IPC-7351B PCB Footprint dimensions for CH342K?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH342K (ESSOP-10-150mil) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.00 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.30 × 3.00 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH342K?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH342K (WCH, ESSOP-10-150mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & CH342 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | UD+ | Digital_IO | Signal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB. |
| 2 | UD- | Digital_IO | Signal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB. |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | VDD5 | Power_In | Primary positive power supply input (VDD5) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 5 | TXD1 | Digital_IO | Signal terminal TXD1 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART. |
| 6 | RXD1 | Digital_IO | Signal terminal RXD1 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART. |
| 7 | VIO | Digital_IO | Signal terminal VIO (I/O, 3.3V to 5V domain). Multiplexed alternate functions: VIO. Supported peripheral buses: General. |
| 8 | TXD0 | Digital_IO | Signal terminal TXD0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART. |
| 9 | RXD0 | Digital_IO | Signal terminal RXD0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART. |
| 10 | V3 | Power_Out | Regulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 11 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |