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MPU-6050 (QFN-24-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

MPU-6050

TDK InvenSenseID: C24112QFN-24-EP(4x4) · 25 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MPU-6050 (QFN-24-EP(4x4))1CLKIN2NC3NC4NC5NC6AUX_DA7AUX_CL8VLOGIC9AD010REGOUT11FSYNC12INT13VDD25EP24SDA23SCL22RESV21RESV20CPOUT19RESV18GND17NC16NC15NC14NCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.222.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1CLKINI/OMultiplexed I/O & Peripheral Pin CLKIN (General)
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
6AUX_DAI/OMultiplexed I/O & Peripheral Pin AUX_DA (General)
7AUX_CLI/OMultiplexed I/O & Peripheral Pin AUX_CL (General)
8VLOGICI/OMultiplexed I/O & Peripheral Pin VLOGIC (General)
9AD0I/OMultiplexed I/O & Peripheral Pin AD0 (General)
10REGOUTI/OMultiplexed I/O & Peripheral Pin REGOUT (General)
11FSYNCI/OMultiplexed I/O & Peripheral Pin FSYNC (General)
12INTI/OMultiplexed I/O & Peripheral Pin INT (General)
13VDDPowerPower Supply Input (VDD — 2.375V-3.46V)
14NCI/OMultiplexed I/O & Peripheral Pin NC (General)
15NCI/OMultiplexed I/O & Peripheral Pin NC (General)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18GNDGNDGround Reference Pin (GND)
19RESVI/OMultiplexed I/O & Peripheral Pin RESV (General)
20CPOUTI/OMultiplexed I/O & Peripheral Pin CPOUT (General)
21RESVI/OMultiplexed I/O & Peripheral Pin RESV (General)
22RESVI/OMultiplexed I/O & Peripheral Pin RESV (General)
23SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
24SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
25EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 CLKIN
I/O
Multiplexed I/O & Peripheral Pin CLKIN (General)
Design note: Signal terminal CLKIN (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: CLKIN. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MPU-6050 (TDK InvenSense · QFN-24-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MPU-6050 (QFN-24-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MPU-6050 (QFN-24-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MPU-6050 (QFN-24-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MPU-6050 (QFN-24-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-24-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
MPU-6050 (QFN-24-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
MPU-6050 (QFN-24-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for MPU
P21 · p21_fig011929×1385px
MPU-6050 (QFN-24-EP(4x4)) — 21 of 52
21 of 52
P21 · p21_fig021774×1216px
MPU-6050 (QFN-24-EP(4x4)) — QFN Package 24-pin, 4mm x 4mm x 0.9mm Orientation of Axes of Sensitivity and
QFN Package 24-pin, 4mm x 4mm x 0.9mm Orientation of Axes of Sensitivity and
P41 · p41_fig012683×1188px
MPU-6050 (QFN-24-EP(4x4)) — On 4 corners - lead dimensions
On 4 corners - lead dimensions
P41 · p41_fig02755×753px
MPU-6050 (QFN-24-EP(4x4)) — D D2
D D2
P41 · p41_fig01P41
MPU-6050 (QFN-24-EP(4x4)) — Datasheet Page 41 (p41_fig01)
Datasheet Page 41 (p41_fig01)
P42 · p42_fig011791×1351px
MPU-6050 (QFN-24-EP(4x4)) — PCB Layout Diagram
PCB Layout Diagram
P42 · p42_fig01P42
MPU-6050 (QFN-24-EP(4x4)) — Datasheet Page 42 (p42_fig01)
Datasheet Page 42 (p42_fig01)

Technical Specifications & Part Details (MPU-6050)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MPU-6050 (QFN-24-EP(4x4)) is a 24-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.375V-3.46V supply operation across -40°C to +85°C with integrated SPI, I2C, ADC interfaces.
Operating Supply VoltageV_CC / V_DD
2.375V-3.46V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
100kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.90 mm (A1=0.04 mm)
Package family: QFN (QFN-24-EP(4x4))
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-24-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.29 × 0.75 mm
Pins / Total PadsTopology
25P / 25Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-24-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MPU-6050 (QFN-24-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MPU-6050 (QFN-24-EP(4x4))?

Manufactured by TDK InvenSense, the MPU-6050 is housed in a QFN-24-EP(4x4) package with 25 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.375V-3.46V. Key pins include: 1 (CLKIN: Multiplexed I/O & Peripheral Pin CLKIN (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (AUX_DA: Multiplexed I/O & Peripheral Pin AUX_DA (General)).

What are the IPC-7351B PCB Footprint dimensions for MPU-6050?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MPU-6050 (QFN-24-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 25 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MPU-6050?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MPU-6050 (TDK InvenSense, QFN-24-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & MPU Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1CLKINDigital_IOSignal terminal CLKIN (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: CLKIN. Supported peripheral buses: General.
2NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6AUX_DADigital_IOSignal terminal AUX_DA (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: AUX_DA. Supported peripheral buses: General.
7AUX_CLDigital_IOSignal terminal AUX_CL (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: AUX_CL. Supported peripheral buses: General.
8VLOGICDigital_IOSignal terminal VLOGIC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: VLOGIC. Supported peripheral buses: General.
9AD0Digital_IOSignal terminal AD0 (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: AD0. Supported peripheral buses: General.
10REGOUTDigital_IOSignal terminal REGOUT (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: REGOUT. Supported peripheral buses: General.
11FSYNCDigital_IOSignal terminal FSYNC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: FSYNC. Supported peripheral buses: General.
12INTDigital_IOSignal terminal INT (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
13VDDPower_InPrimary positive power supply input (VDD) operating in the 2.375V-3.46V domain (Max rating: 3.46V).
14NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
16NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17NCDigital_IOSignal terminal NC (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19RESVDigital_IOSignal terminal RESV (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: RESV. Supported peripheral buses: General.
20CPOUTDigital_IOSignal terminal CPOUT (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: CPOUT. Supported peripheral buses: General.
21RESVDigital_IOSignal terminal RESV (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: RESV. Supported peripheral buses: General.
22RESVDigital_IOSignal terminal RESV (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: RESV. Supported peripheral buses: General.
23SCLDigital_IOSignal terminal SCL (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
24SDADigital_IOSignal terminal SDA (I/O, 2.375V-3.46V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
25EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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