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CH32L103F8U6 (QFN-20-EP(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32L103F8U6

WCHID: C22467836QFN-20-EP(3x3) · 21 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32L103F8U6 (QFN-20-EP(3x3))1PA0/WKUP/ADC2PA1/ADC13PA2/ADC24PA3/ADC35PA4/ADC46PA5/ADC57PA7/ADC78PB0/ADC89PB1/ADC9/PB110PB1111PB6/CC1/PB1321VSS20PA6/ADC619VDD18PA10/T1CH3/P17PA13/SWDIO/P16PA14/SWCLK/P15PA9/T1CH214PA8/T1CH113PB15/T1CH3N12PB14/T1CH2NGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.820.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=3.00mm · Pitch e=0.40mmD=3.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA0/WKUP/ADC0I/OMultiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
2PA1/ADC1I/OMultiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)
3PA2/ADC2I/OMultiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)
4PA3/ADC3I/OMultiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)
5PA4/ADC4I/OMultiplexed I/O & Peripheral Pin PA4/ADC4 (ADC)
6PA5/ADC5I/OMultiplexed I/O & Peripheral Pin PA5/ADC5 (ADC)
7PA7/ADC7I/OMultiplexed I/O & Peripheral Pin PA7/ADC7 (ADC)
8PB0/ADC8I/OMultiplexed I/O & Peripheral Pin PB0/ADC8 (ADC)
9PB1/ADC9/PB10I/OMultiplexed I/O & Peripheral Pin PB1/ADC9/PB10 (ADC)
10PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
11PB6/CC1/PB13/T1CH1NI/OMultiplexed I/O & Peripheral Pin PB6/CC1/PB13/T1CH1N (General)
12PB14/T1CH2NI/OMultiplexed I/O & Peripheral Pin PB14/T1CH2N (General)
13PB15/T1CH3NI/OMultiplexed I/O & Peripheral Pin PB15/T1CH3N (General)
14PA8/T1CH1I/OMultiplexed I/O & Peripheral Pin PA8/T1CH1 (General)
15PA9/T1CH2I/OMultiplexed I/O & Peripheral Pin PA9/T1CH2 (General)
16PA14/SWCLK/PA12/UDPI/OMultiplexed I/O & Peripheral Pin PA14/SWCLK/PA12/UDP (SWD/JTAG)
17PA13/SWDIO/PA11/UDMI/OMultiplexed I/O & Peripheral Pin PA13/SWDIO/PA11/UDM (SWD/JTAG)
18PA10/T1CH3/PB7/CC2I/OMultiplexed I/O & Peripheral Pin PA10/T1CH3/PB7/CC2 (General)
19VDDPowerPower Supply Input (VDD — 1.8V~3.6V)
20PA6/ADC6I/OMultiplexed I/O & Peripheral Pin PA6/ADC6 (ADC)
21VSSGNDGround Reference Pin (VSS)
PIN 1 PA0/WKUP/ADC0
I/O
Multiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)
Design note: Signal terminal PA0/WKUP/ADC0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32L103F8U6 (WCH · QFN-20-EP(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32L103F8U6 (QFN-20-EP(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32L103F8U6 (QFN-20-EP(3x3)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32L103F8U6 (QFN-20-EP(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32L103F8U6 (QFN-20-EP(3x3)) - 4. Package Dimensions (D×E×A)
QFN-20-EP(3x3) · 3.00×3.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32L103F8U6 (QFN-20-EP(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32L103F8U6 (QFN-20-EP(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH32L103
P13 · p13_fig011239×2201px
CH32L103F8U6 (QFN-20-EP(3x3)) — V2.1 11
V2.1 11
P13 · p13_fig01P13
CH32L103F8U6 (QFN-20-EP(3x3)) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)
P15 · p15_fig011138×751px
CH32L103F8U6 (QFN-20-EP(3x3)) — T:TIME_ (T1CH3:TIM1_CH3、T1CH1N:TIM1_CH1N、T1BK:TIM1_BKIN) OPA:OPA_ (OPAP4:OPA_P4、OPAN4:OPA_N4、OPAO2:OPA_O2) UDP:USBDP UDM:USBDM
T:TIME_ (T1CH3:TIM1_CH3、T1CH1N:TIM1_CH1N、T1BK:TIM1_BKIN) OPA:OPA_ (OPAP4:OPA_P4、OPAN4:OPA_N4、OPAO2:OPA_O2) UDP:USBDP UDM:USBDM
P16 · p16_fig011770×2440px
CH32L103F8U6 (QFN-20-EP(3x3)) — V2.1 14
V2.1 14
P37 · p37_fig011961×1379px
CH32L103F8U6 (QFN-20-EP(3x3)) — V2.1 35
V2.1 35
P54 · p54_fig01All Packages in PDF
CH32L103F8U6 (QFN-20-EP(3x3)) — CH32L103/M103 数据手册 https://wch.cn
CH32L103/M103 数据手册 https://wch.cn

Technical Specifications & Part Details (CH32L103F8U6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32L103F8U6 (QFN-20-EP(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V~3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V~3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20-EP(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 1.90×1.90mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20-EP(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20-EP(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32L103F8U6 (QFN-20-EP(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32L103F8U6 (QFN-20-EP(3x3))?

Manufactured by WCH, the CH32L103F8U6 is housed in a QFN-20-EP(3x3) package with 21 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.8V~3.6V. Key pins include: 1 (PA0/WKUP/ADC0: Multiplexed I/O & Peripheral Pin PA0/WKUP/ADC0 (ADC)), 2 (PA1/ADC1: Multiplexed I/O & Peripheral Pin PA1/ADC1 (ADC)), 3 (PA2/ADC2: Multiplexed I/O & Peripheral Pin PA2/ADC2 (ADC)), 4 (PA3/ADC3: Multiplexed I/O & Peripheral Pin PA3/ADC3 (ADC)), 5 (PA4/ADC4: Multiplexed I/O & Peripheral Pin PA4/ADC4 (ADC)), 6 (PA5/ADC5: Multiplexed I/O & Peripheral Pin PA5/ADC5 (ADC)).

What are the IPC-7351B PCB Footprint dimensions for CH32L103F8U6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32L103F8U6 (QFN-20-EP(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.40 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.90 × 1.90 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32L103F8U6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32L103F8U6 (WCH, QFN-20-EP(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & CH32L103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA0/WKUP/ADC0AnalogSignal terminal PA0/WKUP/ADC0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA0/WKUP/ADC0. Supported peripheral buses: ADC.
2PA1/ADC1AnalogSignal terminal PA1/ADC1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA1/ADC1. Supported peripheral buses: ADC.
3PA2/ADC2AnalogSignal terminal PA2/ADC2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA2/ADC2. Supported peripheral buses: ADC.
4PA3/ADC3AnalogSignal terminal PA3/ADC3 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA3/ADC3. Supported peripheral buses: ADC.
5PA4/ADC4AnalogSignal terminal PA4/ADC4 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA4/ADC4. Supported peripheral buses: ADC.
6PA5/ADC5AnalogSignal terminal PA5/ADC5 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA5/ADC5. Supported peripheral buses: ADC.
7PA7/ADC7AnalogSignal terminal PA7/ADC7 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA7/ADC7. Supported peripheral buses: ADC.
8PB0/ADC8AnalogSignal terminal PB0/ADC8 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB0/ADC8. Supported peripheral buses: ADC.
9PB1/ADC9/PB10AnalogSignal terminal PB1/ADC9/PB10 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB1/ADC9/PB10. Supported peripheral buses: ADC.
10PB11Digital_IOSignal terminal PB11 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
11PB6/CC1/PB13/T1CH1NDigital_IOSignal terminal PB6/CC1/PB13/T1CH1N (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB6/CC1/PB13/T1CH1N. Supported peripheral buses: General.
12PB14/T1CH2NDigital_IOSignal terminal PB14/T1CH2N (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB14/T1CH2N. Supported peripheral buses: General.
13PB15/T1CH3NDigital_IOSignal terminal PB15/T1CH3N (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB15/T1CH3N. Supported peripheral buses: General.
14PA8/T1CH1Digital_IOSignal terminal PA8/T1CH1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA8/T1CH1. Supported peripheral buses: General.
15PA9/T1CH2Digital_IOSignal terminal PA9/T1CH2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA9/T1CH2. Supported peripheral buses: General.
16PA14/SWCLK/PA12/UDPDigital_IOSignal terminal PA14/SWCLK/PA12/UDP (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA14/SWCLK/PA12/UDP. Supported peripheral buses: SWD/JTAG.
17PA13/SWDIO/PA11/UDMDigital_IOSignal terminal PA13/SWDIO/PA11/UDM (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA13/SWDIO/PA11/UDM. Supported peripheral buses: SWD/JTAG.
18PA10/T1CH3/PB7/CC2Digital_IOSignal terminal PA10/T1CH3/PB7/CC2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA10/T1CH3/PB7/CC2. Supported peripheral buses: General.
19VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8V~3.6V domain (Max rating: 3.6V).
20PA6/ADC6AnalogSignal terminal PA6/ADC6 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA6/ADC6. Supported peripheral buses: ADC.
21VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
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