QFN-20-EP(3x3) · 21P
Synchronized Pinout (Symbol / 2D / 3D) (48/48)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VBAT | Power | Power Supply Input (VBAT — 1.8V~3.6V) |
| 2 | PC13/TAMPER/RTC | I/O | Multiplexed I/O & Peripheral Pin PC13/TAMPER/RTC (RTC/CLK) |
| 3 | PC14/OSC32IN | I/O | Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK) |
| 4 | PC15/OSC32OUT | I/O | Multiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK) |
| 5 | OSC_IN/PD0 | I/O | Multiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK) |
| 6 | OSC_OUT/PD1 | I/O | Multiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK) |
| 7 | NRST | I | System Enable & Hardware Reset (NRST) |
| 8 | VSSA | GND | Ground Reference Pin (VSSA) |
| 9 | VDDA | Power | Power Supply Input (VDDA — 1.8V~3.6V) |
| 10 | PA0/WKUP/ADC0/OPAP4 | I/O | Multiplexed I/O & Peripheral Pin PA0/WKUP/ADC0/OPAP4 (ADC) |
| 11 | PA1/ADC1/OPAN4 | I/O | Multiplexed I/O & Peripheral Pin PA1/ADC1/OPAN4 (ADC) |
| 12 | PA2/ADC2/OPAO2 | I/O | Multiplexed I/O & Peripheral Pin PA2/ADC2/OPAO2 (ADC) |
| 13 | PA3/ADC3/OPAO0 | I/O | Multiplexed I/O & Peripheral Pin PA3/ADC3/OPAO0 (ADC) |
| 14 | PA4/ADC4/OPAO3 | I/O | Multiplexed I/O & Peripheral Pin PA4/ADC4/OPAO3 (ADC) |
| 15 | PA5/ADC5/OPAN3 | I/O | Multiplexed I/O & Peripheral Pin PA5/ADC5/OPAN3 (ADC) |
| 16 | PA6/ADC6/OPAP5/OPAN1 | I/O | Multiplexed I/O & Peripheral Pin PA6/ADC6/OPAP5/OPAN1 (ADC) |
| 17 | PA7/ADC7/OPAP3/OPAN5 | I/O | Multiplexed I/O & Peripheral Pin PA7/ADC7/OPAP3/OPAN5 (ADC) |
| 18 | PB0/ADC8/OPAP1/OPAO4 | I/O | Multiplexed I/O & Peripheral Pin PB0/ADC8/OPAP1/OPAO4 (ADC) |
| 19 | PB1/ADC9/OPAO1 | I/O | Multiplexed I/O & Peripheral Pin PB1/ADC9/OPAO1 (ADC) |
| 20 | PB2/BOOT1 | I/O | Multiplexed I/O & Peripheral Pin PB2/BOOT1 (General) |
| 21 | PB10/OPAN2/OPAN6 | I/O | Multiplexed I/O & Peripheral Pin PB10/OPAN2/OPAN6 (General) |
| 22 | PB11/OPAN0 | I/O | Multiplexed I/O & Peripheral Pin PB11/OPAN0 (General) |
| 23 | VSS | GND | Ground Reference Pin (VSS) |
| 24 | VDD | Power | Power Supply Input (VDD — 1.8V~3.6V) |
| 25 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (General) |
| 26 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (General) |
| 27 | PB14/OPAP2 | I/O | Multiplexed I/O & Peripheral Pin PB14/OPAP2 (General) |
| 28 | PB15/OPAP0 | I/O | Multiplexed I/O & Peripheral Pin PB15/OPAP0 (General) |
| 29 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| 30 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (General) |
| 31 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 32 | PA11/UDM | I/O | Multiplexed I/O & Peripheral Pin PA11/UDM (General) |
| 33 | PA12/UDP | I/O | Multiplexed I/O & Peripheral Pin PA12/UDP (General) |
| 34 | PA13/SWDIO | I/O | Multiplexed I/O & Peripheral Pin PA13/SWDIO (SWD/JTAG) |
| 35 | VSS | GND | Ground Reference Pin (VSS) |
| 36 | VDD | Power | Power Supply Input (VDD — 1.8V~3.6V) |
| 37 | PA14/SWCLK | I/O | Multiplexed I/O & Peripheral Pin PA14/SWCLK (SWD/JTAG) |
| 38 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (General) |
| 39 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| 40 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| 41 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| 42 | PB6/CC1 | I/O | Multiplexed I/O & Peripheral Pin PB6/CC1 (General) |
| 43 | PB7/CC2 | I/O | Multiplexed I/O & Peripheral Pin PB7/CC2 (General) |
| 44 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| 45 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| 46 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (General) |
| 47 | VSS | GND | Ground Reference Pin (VSS) |
| 48 | VDD | Power | Power Supply Input (VDD — 1.8V~3.6V) |
PIN 1 VBAT
PowerPower Supply Input (VBAT — 1.8V~3.6V)
Design note: Primary positive power supply input (VBAT) operating in the 1.8V~3.6V domain (Max rating: 3.6V).
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH32L103
P54 · p54_fig01EXACT PACKAGE
P13 · p13_fig011239×2201px
P13 · p13_fig01P13
P15 · p15_fig011138×751px
P16 · p16_fig011770×2440px
P37 · p37_fig011961×1379px
Technical Specifications & Part Details (CH32L103C8T6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH32L103C8T6 (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V~3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V~3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2/BOOT1, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol48 auto-grouped pins
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH32L103 (3)
QFN-32(4x4) · 33P
LQFP-48(7x7) · 48P
Mechanical Dimensions & Land Pattern (LQFP-48(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-48(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH32L103C8T6 (LQFP-48(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH32L103C8T6 (LQFP-48(7x7))?
Manufactured by WCH, the CH32L103C8T6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V~3.6V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 1.8V~3.6V)), 2 (PC13/TAMPER/RTC: Multiplexed I/O & Peripheral Pin PC13/TAMPER/RTC (RTC/CLK)), 3 (PC14/OSC32IN: Multiplexed I/O & Peripheral Pin PC14/OSC32IN (RTC/CLK)), 4 (PC15/OSC32OUT: Multiplexed I/O & Peripheral Pin PC15/OSC32OUT (RTC/CLK)), 5 (OSC_IN/PD0: Multiplexed I/O & Peripheral Pin OSC_IN/PD0 (RTC/CLK)), 6 (OSC_OUT/PD1: Multiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for CH32L103C8T6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32L103C8T6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32L103C8T6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32L103C8T6 (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (48 pins) & CH32L103 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 1.8V~3.6V domain (Max rating: 3.6V). |
| 2 | PC13/TAMPER/RTC | Digital_IO | Signal terminal PC13/TAMPER/RTC (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PC13/TAMPER/RTC. Supported peripheral buses: RTC/CLK. |
| 3 | PC14/OSC32IN | Digital_IO | Signal terminal PC14/OSC32IN (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PC14/OSC32IN. Supported peripheral buses: RTC/CLK. |
| 4 | PC15/OSC32OUT | Digital_IO | Signal terminal PC15/OSC32OUT (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PC15/OSC32OUT. Supported peripheral buses: RTC/CLK. |
| 5 | OSC_IN/PD0 | Digital_IO | Signal terminal OSC_IN/PD0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: OSC_IN/PD0. Supported peripheral buses: RTC/CLK. |
| 6 | OSC_OUT/PD1 | Digital_IO | Signal terminal OSC_OUT/PD1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: OSC_OUT/PD1. Supported peripheral buses: RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 1.8V~3.6V domain (Max rating: 3.6V). |
| 10 | PA0/WKUP/ADC0/OPAP4 | Analog | Signal terminal PA0/WKUP/ADC0/OPAP4 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA0/WKUP/ADC0/OPAP4. Supported peripheral buses: ADC. |
| 11 | PA1/ADC1/OPAN4 | Analog | Signal terminal PA1/ADC1/OPAN4 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA1/ADC1/OPAN4. Supported peripheral buses: ADC. |
| 12 | PA2/ADC2/OPAO2 | Analog | Signal terminal PA2/ADC2/OPAO2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA2/ADC2/OPAO2. Supported peripheral buses: ADC. |
| 13 | PA3/ADC3/OPAO0 | Analog | Signal terminal PA3/ADC3/OPAO0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA3/ADC3/OPAO0. Supported peripheral buses: ADC. |
| 14 | PA4/ADC4/OPAO3 | Analog | Signal terminal PA4/ADC4/OPAO3 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA4/ADC4/OPAO3. Supported peripheral buses: ADC. |
| 15 | PA5/ADC5/OPAN3 | Analog | Signal terminal PA5/ADC5/OPAN3 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA5/ADC5/OPAN3. Supported peripheral buses: ADC. |
| 16 | PA6/ADC6/OPAP5/OPAN1 | Analog | Signal terminal PA6/ADC6/OPAP5/OPAN1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA6/ADC6/OPAP5/OPAN1. Supported peripheral buses: ADC. |
| 17 | PA7/ADC7/OPAP3/OPAN5 | Analog | Signal terminal PA7/ADC7/OPAP3/OPAN5 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA7/ADC7/OPAP3/OPAN5. Supported peripheral buses: ADC. |
| 18 | PB0/ADC8/OPAP1/OPAO4 | Analog | Signal terminal PB0/ADC8/OPAP1/OPAO4 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB0/ADC8/OPAP1/OPAO4. Supported peripheral buses: ADC. |
| 19 | PB1/ADC9/OPAO1 | Analog | Signal terminal PB1/ADC9/OPAO1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB1/ADC9/OPAO1. Supported peripheral buses: ADC. |
| 20 | PB2/BOOT1 | Digital_IO | Signal terminal PB2/BOOT1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB2/BOOT1. Supported peripheral buses: General. |
| 21 | PB10/OPAN2/OPAN6 | Digital_IO | Signal terminal PB10/OPAN2/OPAN6 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB10/OPAN2/OPAN6. Supported peripheral buses: General. |
| 22 | PB11/OPAN0 | Digital_IO | Signal terminal PB11/OPAN0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB11/OPAN0. Supported peripheral buses: General. |
| 23 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 1.8V~3.6V domain (Max rating: 3.6V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General. |
| 26 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General. |
| 27 | PB14/OPAP2 | Digital_IO | Signal terminal PB14/OPAP2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB14/OPAP2. Supported peripheral buses: General. |
| 28 | PB15/OPAP0 | Digital_IO | Signal terminal PB15/OPAP0 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB15/OPAP0. Supported peripheral buses: General. |
| 29 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General. |
| 30 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General. |
| 31 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 32 | PA11/UDM | Digital_IO | Signal terminal PA11/UDM (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA11/UDM. Supported peripheral buses: General. |
| 33 | PA12/UDP | Digital_IO | Signal terminal PA12/UDP (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA12/UDP. Supported peripheral buses: General. |
| 34 | PA13/SWDIO | Digital_IO | Signal terminal PA13/SWDIO (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA13/SWDIO. Supported peripheral buses: SWD/JTAG. |
| 35 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 1.8V~3.6V domain (Max rating: 3.6V). |
| 37 | PA14/SWCLK | Digital_IO | Signal terminal PA14/SWCLK (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA14/SWCLK. Supported peripheral buses: SWD/JTAG. |
| 38 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General. |
| 39 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |
| 40 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| 41 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| 42 | PB6/CC1 | Digital_IO | Signal terminal PB6/CC1 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB6/CC1. Supported peripheral buses: General. |
| 43 | PB7/CC2 | Digital_IO | Signal terminal PB7/CC2 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB7/CC2. Supported peripheral buses: General. |
| 44 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 1.8V~3.6V domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| 45 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General. |
| 46 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 1.8V~3.6V domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General. |
| 47 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 1.8V~3.6V domain (Max rating: 3.6V). |