Mechanical Dimensions & Land Pattern (SOIC-14)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SOIC-14 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ATTINY24-20SSU (SOIC-14)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ATTINY24-20SSU (SOIC-14)?
Manufactured by MICROCHIP, the ATTINY24-20SSU is housed in a SOIC-14 package with 14 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 1 (1: Multiplexed I/O & Peripheral Pin 1 (I2C)), 2 ((PCINT8/XTAL1/CLKI)PB0: Multiplexed I/O & Peripheral Pin (PCINT8/XTAL1/CLKI)PB0 (RTC/CLK)), 3 ((PCINT9/XTAL2)PB1: Multiplexed I/O & Peripheral Pin (PCINT9/XTAL2)PB1 (RTC/CLK)), 4 ((PCINT11/#RESET/dW)PB3: System Enable & Hardware Reset ((PCINT11/#RESET/dW)PB3)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for ATTINY24-20SSU?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATTINY24-20SSU (SOIC-14) has a nominal body envelope of 3.90 × 8.65 mm, pitch e = 1.27 mm, and 14 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATTINY24-20SSU?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATTINY24-20SSU (MICROCHIP, SOIC-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (14 pins) & ATTINY24 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | 1 | Digital_IO | Signal terminal 1 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: 1. Supported peripheral buses: I2C. |
| 2 | (PCINT8/XTAL1/CLKI)PB0 | Digital_IO | Signal terminal (PCINT8/XTAL1/CLKI)PB0 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: (PCINT8/XTAL1/CLKI)PB0. Supported peripheral buses: RTC/CLK. |
| 3 | (PCINT9/XTAL2)PB1 | Digital_IO | Signal terminal (PCINT9/XTAL2)PB1 (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: (PCINT9/XTAL2)PB1. Supported peripheral buses: RTC/CLK. |
| 4 | (PCINT11/#RESET/dW)PB3 | Digital_IO | Active-low hardware reset terminal ((PCINT11/#RESET/dW)PB3): pulling this pin Low resets the processor core and peripherals. |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | NC | No_Connect | No Connect (Leave Floating) |
| 8 | IO0 | Digital_IO | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | PA3(ADC3/T0/PCINT3) | Analog | Signal terminal PA3(ADC3/T0/PCINT3) (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: PA3(ADC3/T0/PCINT3). Supported peripheral buses: ADC. |
| 11 | PA2(ADC2/AIN1/PCINT2) | Analog | Signal terminal PA2(ADC2/AIN1/PCINT2) (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: PA2(ADC2/AIN1/PCINT2). Supported peripheral buses: ADC. |
| 12 | PA1(ADC1/AIN0/PCINT1) | Analog | Signal terminal PA1(ADC1/AIN0/PCINT1) (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: PA1(ADC1/AIN0/PCINT1). Supported peripheral buses: ADC. |
| 13 | PA0(ADC0/AREF/PCINT0) | Analog | Signal terminal PA0(ADC0/AREF/PCINT0) (I/O, 1.8V to 5.5V domain). Multiplexed alternate functions: PA0(ADC0/AREF/PCINT0). Supported peripheral buses: ADC. |
| 14 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |