PIC24FJ128GA606-I/PT (TQFP-64(10x10)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC24FJ128GA606-I/PT (TQFP-64(10x10))?

Manufactured by MICROCHIP, the PIC24FJ128GA606-I/PT is housed in a TQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0V to 3.6V. Key pins include: 1 (D3: Multiplexed I/O & Peripheral Pin D3 (General)), 2 (C1: Multiplexed I/O & Peripheral Pin C1 (I2C)), 3 (D2: Multiplexed I/O & Peripheral Pin D2 (I2C)), 4 (E3: Multiplexed I/O & Peripheral Pin E3 (General)), 5 (F4: Multiplexed I/O & Peripheral Pin F4 (General)), 6 (F2: Multiplexed I/O & Peripheral Pin F2 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC24FJ128GA606-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24FJ128GA606-I/PT (TQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24FJ128GA606-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24FJ128GA606-I/PT (MICROCHIP, TQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	D3	I/O	Multiplexed I/O & Peripheral Pin D3 (General)
2	C1	I/O	Multiplexed I/O & Peripheral Pin C1 (I2C)
3	D2	I/O	Multiplexed I/O & Peripheral Pin D2 (I2C)
4	E3	I/O	Multiplexed I/O & Peripheral Pin E3 (General)
5	F4	I/O	Multiplexed I/O & Peripheral Pin F4 (General)
6	F2	I/O	Multiplexed I/O & Peripheral Pin F2 (General)
7	F1	I/O	Multiplexed I/O & Peripheral Pin F1 (General)
8	F3	I/O	Multiplexed I/O & Peripheral Pin F3 (General)
9	VSS	GND	Ground Reference Pin (VSS)
10	VDD	Power	Power Supply Input (VDD — 2.0V to 3.6V)
11	H1	I/O	Multiplexed I/O & Peripheral Pin H1 (General)
12	H2	I/O	Multiplexed I/O & Peripheral Pin H2 (General)
13	J1	I/O	Multiplexed I/O & Peripheral Pin J1 (General)
14	J2	I/O	Multiplexed I/O & Peripheral Pin J2 (General)
15	K1L2 ,	I/O	Multiplexed I/O & Peripheral Pin K1L2 , (General)
16	K2K3 ,	I/O	Multiplexed I/O & Peripheral Pin K2K3 , (General)
17	L1	I/O	Multiplexed I/O & Peripheral Pin L1 (General)
18	J3	I/O	Multiplexed I/O & Peripheral Pin J3 (General)
19	J4	I/O	Multiplexed I/O & Peripheral Pin J4 (General)
20	L3	I/O	Multiplexed I/O & Peripheral Pin L3 (General)
21	K4	I/O	Multiplexed I/O & Peripheral Pin K4 (General)
22	L4	I/O	Multiplexed I/O & Peripheral Pin L4 (General)
23	G3	I/O	Multiplexed I/O & Peripheral Pin G3 (General)
24	G9	I/O	Multiplexed I/O & Peripheral Pin G9 (General)
25	VSS	GND	Ground Reference Pin (VSS)
26	VDD	Power	Power Supply Input (VDD — 2.0V to 3.6V)
27	J7	I/O	Multiplexed I/O & Peripheral Pin J7 (General)
28	G11	I/O	Multiplexed I/O & Peripheral Pin G11 (General)
29	K7	I/O	Multiplexed I/O & Peripheral Pin K7 (General)
30	L8	I/O	Multiplexed I/O & Peripheral Pin L8 (General)
31	G10	I/O	Multiplexed I/O & Peripheral Pin G10 (I2C)
32	H11	I/O	Multiplexed I/O & Peripheral Pin H11 (I2C)
33	K10	I/O	Multiplexed I/O & Peripheral Pin K10 (General)
34	K11	I/O	Multiplexed I/O & Peripheral Pin K11 (General)
35	H9	I/O	Multiplexed I/O & Peripheral Pin H9 (General)
36	J11	I/O	Multiplexed I/O & Peripheral Pin J11 (I2C)
37	H10	I/O	Multiplexed I/O & Peripheral Pin H10 (I2C)
38	VDD	Power	Power Supply Input (VDD — 2.0V to 3.6V)
39	F9	I/O	Multiplexed I/O & Peripheral Pin F9 (General)
40	F11	I/O	Multiplexed I/O & Peripheral Pin F11 (General)
41	VSS	GND	Ground Reference Pin (VSS)
42	E9	I/O	Multiplexed I/O & Peripheral Pin E9 (General)
43	E10	I/O	Multiplexed I/O & Peripheral Pin E10 (General)
44	D11	I/O	Multiplexed I/O & Peripheral Pin D11 (General)
45	C11	I/O	Multiplexed I/O & Peripheral Pin C11 (General)
46	D9	I/O	Multiplexed I/O & Peripheral Pin D9 (General)
47	C10	I/O	Multiplexed I/O & Peripheral Pin C10 (General)
48	B11	I/O	Multiplexed I/O & Peripheral Pin B11 (General)
49	A11	I/O	Multiplexed I/O & Peripheral Pin A11 (General)
50	A10	I/O	Multiplexed I/O & Peripheral Pin A10 (General)
51	B9	I/O	Multiplexed I/O & Peripheral Pin B9 (General)
52	C8	I/O	Multiplexed I/O & Peripheral Pin C8 (General)
53	B8	I/O	Multiplexed I/O & Peripheral Pin B8 (General)
54	D7	I/O	Multiplexed I/O & Peripheral Pin D7 (General)
55	C7	I/O	Multiplexed I/O & Peripheral Pin C7 (General)
56	B7	I/O	Multiplexed I/O & Peripheral Pin B7 (General)
57	N/C	I/O	Multiplexed I/O & Peripheral Pin N/C (General)
58	B6	I/O	Multiplexed I/O & Peripheral Pin B6 (General)
59	A6	I/O	Multiplexed I/O & Peripheral Pin A6 (General)
60	A4	I/O	Multiplexed I/O & Peripheral Pin A4 (General)
61	B4	I/O	Multiplexed I/O & Peripheral Pin B4 (General)
62	B3	I/O	Multiplexed I/O & Peripheral Pin B3 (General)
63	A2	I/O	Multiplexed I/O & Peripheral Pin A2 (General)
64	A1	I/O	Multiplexed I/O & Peripheral Pin A1 (General)

PIN 1 D3

I/O

Multiplexed I/O & Peripheral Pin D3 (General)

Design note: RE5

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) - 2. Standard Pinout (Top View)

True package pinout (64 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) - 4. Package Dimensions (D×E×A)

TQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) - 5. Recommended Land Pattern

IPC-7351B Footprint (64 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)

Showing 1–12 of 13 uncropped original figures for PIC24FJ128GA

P1 · p01_fig01377×200px

16-Bit Microcontrollers with Large, Dual Partition Flash Program Memory and USB On-The-Go (OTG)

P4 · p04_fig011053×1024px

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) — 2 3 4 5 6 7 8 9 10 11 12 | 13 14 15 16 | 48 47 | 22 | 44 | 24 25 26 27 28 29 30 31 32 | 1 | 46 | 45 | 23 | 43 42 | 41 | 40 39 | 63 62 61 | 59 60 | 58 57 56 | 54 55 | 53 52 51 | 49 50 | 38 | 37 | 34 | 36 35 | 33 | 17 | 19 20 21 | 18 64 | VDD

2 3 4 5 6 7 8 9 10 11 12 | 13 14 15 16 | 48 47 | 22 | 44 | 24 25 26 27 28 29 30 31 32 | 1 | 46 | 45 | 23 | 43 42 | 41 | 40 39 | 63 62 61 | 59 60 | 58 57 56 | 54 55 | 53 52 51 | 49 50 | 38 | 37 | 34 | 36 35 | 33 | 17 | 19 20 21 | 18 64 | VDD

P6 · p06_fig011053×1030px

2 3 4 | 5 6 7 8 9 10 11 12 13 14 | 15 16 | 48 47 | 22 | 44 | 24 25 26 27 28 29 30 31 32 | 1 | 46 45 | 23 | 43 42 41 | 40 39 | 63 62 61 | 59 60 | 58 57 56 | 54 55 | 53 52 51 | 49 50 | 38 37 | 34 | 36 35 | 33 | 17 | 19 20 21 | 18 64 | VDD | V

P6 · p06_fig01P6

Datasheet Page 6 (p06_fig01)

P42 · p42_fig01867×940px

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS

P372 · p372_fig01925×832px

FIGURE 28-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT

P372 · p372_fig01P372

Datasheet Page 372 (p372_fig01)

P373 · p373_fig01967×656px

FIGURE 28-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT (TGEN = 0)

P373 · p373_fig021029×666px

FIGURE 28-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION (TGEN = 1)

P451 · p451_fig011778×2732px

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) —  2015-2018 Microchip Technology Inc. DS30010074F-page 451 | PIC24FJ1024GA610/GB610 FAMILY | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: | 64-Le

 2015-2018 Microchip Technology Inc. DS30010074F-page 451 | PIC24FJ1024GA610/GB610 FAMILY | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: | 64-Le

P452 · p452_fig011778×2732px

PIC24FJ128GA606-I/PT (TQFP-64(10x10)) — PIC24FJ1024GA610/GB610 FAMILY | DS30010074F-page 452  2015-2018 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.

PIC24FJ1024GA610/GB610 FAMILY | DS30010074F-page 452  2015-2018 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.

P452 · p452_fig01P452

Datasheet Page 452 (p452_fig01)

Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (PIC24FJ128GA606-I/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC24FJ128GA606-I/PT (TQFP-64(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.0V to 3.6V supply operation across -40°C to +85°C with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA interfaces.

Operating Supply VoltageV_CC / V_DD

2.0V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

32 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

10.00 × 10.00 × 1.20 mm (A1=0.10 mm)

Package family: TQFP (TQFP-64(10x10))

Pin Count & Lead PitchN / e

64 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol64 auto-grouped pins

IPC-7351B Land Pattern64 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

10.00 × 10.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.20mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.50 mm

Pins / Total PadsTopology

64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TQFP-64(10x10)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC24FJ128GA606-I/PT (TQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC24FJ128GA606-I/PT (TQFP-64(10x10))?

Manufactured by MICROCHIP, the PIC24FJ128GA606-I/PT is housed in a TQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0V to 3.6V. Key pins include: 1 (D3: Multiplexed I/O & Peripheral Pin D3 (General)), 2 (C1: Multiplexed I/O & Peripheral Pin C1 (I2C)), 3 (D2: Multiplexed I/O & Peripheral Pin D2 (I2C)), 4 (E3: Multiplexed I/O & Peripheral Pin E3 (General)), 5 (F4: Multiplexed I/O & Peripheral Pin F4 (General)), 6 (F2: Multiplexed I/O & Peripheral Pin F2 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC24FJ128GA606-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24FJ128GA606-I/PT (TQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24FJ128GA606-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24FJ128GA606-I/PT (MICROCHIP, TQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & PIC24FJ128GA Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	D3	Digital_IO	Signal terminal D3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
2	C1	Digital_IO	Signal terminal C1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: C1. Supported peripheral buses: I2C.
3	D2	Digital_IO	Signal terminal D2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: D2. Supported peripheral buses: I2C.
4	E3	Digital_IO	Signal terminal E3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: E3. Supported peripheral buses: General.
5	F4	Digital_IO	Signal terminal F4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: F4. Supported peripheral buses: General.
6	F2	Digital_IO	Signal terminal F2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: F2. Supported peripheral buses: General.
7	F1	Digital_IO	Signal terminal F1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: F1. Supported peripheral buses: General.
8	F3	Digital_IO	Signal terminal F3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: F3. Supported peripheral buses: General.
9	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
10	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V).
11	H1	Digital_IO	Signal terminal H1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: H1. Supported peripheral buses: General.
12	H2	Digital_IO	Signal terminal H2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: H2. Supported peripheral buses: General.
13	J1	Digital_IO	Signal terminal J1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: J1. Supported peripheral buses: General.
14	J2	Digital_IO	Signal terminal J2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: J2. Supported peripheral buses: General.
15	K1L2 ,	Digital_IO	Signal terminal K1L2 , (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: K1L2 ,. Supported peripheral buses: General.
16	K2K3 ,	Digital_IO	Signal terminal K2K3 , (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: K2K3 ,. Supported peripheral buses: General.
17	L1	Digital_IO	Signal terminal L1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: L1. Supported peripheral buses: General.
18	J3	Digital_IO	Signal terminal J3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: J3. Supported peripheral buses: General.
19	J4	Digital_IO	Signal terminal J4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: J4. Supported peripheral buses: General.
20	L3	Digital_IO	Signal terminal L3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: L3. Supported peripheral buses: General.
21	K4	Digital_IO	Signal terminal K4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: K4. Supported peripheral buses: General.
22	L4	Digital_IO	Signal terminal L4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: L4. Supported peripheral buses: General.
23	G3	Digital_IO	Signal terminal G3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: G3. Supported peripheral buses: General.
24	G9	Digital_IO	Signal terminal G9 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: G9. Supported peripheral buses: General.
25	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
26	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V).
27	J7	Digital_IO	Signal terminal J7 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: J7. Supported peripheral buses: General.
28	G11	Digital_IO	Signal terminal G11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: G11. Supported peripheral buses: General.
29	K7	Digital_IO	Signal terminal K7 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: K7. Supported peripheral buses: General.
30	L8	Digital_IO	Signal terminal L8 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: L8. Supported peripheral buses: General.
31	G10	Digital_IO	Signal terminal G10 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: G10. Supported peripheral buses: I2C.
32	H11	Digital_IO	Signal terminal H11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: H11. Supported peripheral buses: I2C.
33	K10	Digital_IO	Signal terminal K10 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: K10. Supported peripheral buses: General.
34	K11	Digital_IO	Signal terminal K11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: K11. Supported peripheral buses: General.
35	H9	Digital_IO	Signal terminal H9 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: H9. Supported peripheral buses: General.
36	J11	Digital_IO	Signal terminal J11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: J11. Supported peripheral buses: I2C.
37	H10	Digital_IO	Signal terminal H10 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: H10. Supported peripheral buses: I2C.
38	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V).
39	F9	Digital_IO	Signal terminal F9 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: F9. Supported peripheral buses: General.
40	F11	Digital_IO	Signal terminal F11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: F11. Supported peripheral buses: General.
41	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
42	E9	Digital_IO	Signal terminal E9 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: U6RTS. Supported peripheral buses: General.
43	E10	Digital_IO	Signal terminal E10 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: E10. Supported peripheral buses: General.
44	D11	Digital_IO	Signal terminal D11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: D11. Supported peripheral buses: General.
45	C11	Digital_IO	Signal terminal C11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: C11. Supported peripheral buses: General.
46	D9	Digital_IO	Signal terminal D9 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: U6CTS. Supported peripheral buses: General.
47	C10	Digital_IO	Signal terminal C10 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: C10. Supported peripheral buses: General.
48	B11	Digital_IO	Signal terminal B11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: B11. Supported peripheral buses: General.
49	A11	Digital_IO	Signal terminal A11 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
50	A10	Digital_IO	Signal terminal A10 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
51	B9	Digital_IO	Signal terminal B9 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: B9. Supported peripheral buses: General.
52	C8	Digital_IO	Signal terminal C8 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: C8. Supported peripheral buses: General.
53	B8	Digital_IO	Signal terminal B8 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: B8. Supported peripheral buses: General.
54	D7	Digital_IO	Signal terminal D7 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
55	C7	Digital_IO	Signal terminal C7 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: U5RTS. Supported peripheral buses: General.
56	B7	Digital_IO	Signal terminal B7 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: B7. Supported peripheral buses: General.
57	N/C	Digital_IO	Signal terminal N/C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
58	B6	Digital_IO	Signal terminal B6 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: U5CTS. Supported peripheral buses: General.
59	A6	Digital_IO	Signal terminal A6 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
60	A4	Digital_IO	Signal terminal A4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
61	B4	Digital_IO	Signal terminal B4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: B4. Supported peripheral buses: General.
62	B3	Digital_IO	Signal terminal B3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: B3. Supported peripheral buses: General.
63	A2	Digital_IO	Signal terminal A2 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
64	A1	Digital_IO	Signal terminal A1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.

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