![DSPIC33FJ128GP802-I/SO (SOIC-28-300mil) — dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 | 28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body [QFN-S] with 0.40 mm Contact Length | Note: For the most current package drawings, please see the Micr](/api/v1/assets/C219562/extracted/figures/p412_fig01.png)
Mechanical Dimensions & Land Pattern (SOIC-28-300mil)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SOIC-28-300mil | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — DSPIC33FJ128GP802-I/SO (SOIC-28-300mil)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of DSPIC33FJ128GP802-I/SO (SOIC-28-300mil)?
Manufactured by MICROCHIP, the DSPIC33FJ128GP802-I/SO is housed in a SOIC-28-300mil package with 28 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (MCLR#: Multiplexed I/O & Peripheral Pin MCLR# (General)), 2 (AN0/VREF+/CN2/RA0: Multiplexed I/O & Peripheral Pin AN0/VREF+/CN2/RA0 (General)), 3 (AN1/VREF-/CN3/RA1: Multiplexed I/O & Peripheral Pin AN1/VREF-/CN3/RA1 (General)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for DSPIC33FJ128GP802-I/SO?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DSPIC33FJ128GP802-I/SO (SOIC-28-300mil) has a nominal body envelope of 7.50 × 17.90 mm, pitch e = 1.27 mm, and 28 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DSPIC33FJ128GP802-I/SO?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DSPIC33FJ128GP802-I/SO (MICROCHIP, SOIC-28-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (28 pins) & DSPIC33FJ128 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | MCLR# | Digital_IO | Signal terminal MCLR# (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General. |
| 2 | AN0/VREF+/CN2/RA0 | Analog | Signal terminal AN0/VREF+/CN2/RA0 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN0/VREF+/CN2/RA0. Supported peripheral buses: General. |
| 3 | AN1/VREF-/CN3/RA1 | Analog | Signal terminal AN1/VREF-/CN3/RA1 (Analog, 3.0V to 3.6V domain). Multiplexed alternate functions: AN1/VREF-/CN3/RA1. Supported peripheral buses: General. |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | NC | No_Connect | No Connect (Leave Floating) |
| 8 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | OSC1/CLKI/CN30/RA2 | Digital_IO | Signal terminal OSC1/CLKI/CN30/RA2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/CN30/RA2. Supported peripheral buses: RTC/CLK. |
| 10 | IO5 | Digital_IO | GPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4 |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V). |
| 14 | IO16 | Digital_IO | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | Digital_IO | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | Digital_IO | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 20 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V). |
| 21 | IO10 | Digital_IO | GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0 |
| 22 | IO11 | Digital_IO | GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID |
| 23 | IO12 | Digital_IO | GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK |
| 24 | IO13 | Digital_IO | GPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ |
| 25 | IO14 | Digital_IO | GPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP |
| 26 | IO21 | Digital_IO | GPIO21 / RTC_GPIO21 |
| 27 | AVSS | GND | 0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 28 | AVDD | Power_In | Primary positive power supply input (AVDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V). |