PIC18F1320-I/SO (SOIC-18-300mil) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC18F1320-I/SO (SOIC-18-300mil)?

Manufactured by MICROCHIP, the PIC18F1320-I/SO is housed in a SOIC-18-300mil package with 18 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 2 (RA1/AN1/LVDIN: Multiplexed I/O & Peripheral Pin RA1/AN1/LVDIN (General)), 3 (RA4/T0CKI: Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)), 4 (MCLR#/VPP/RA5: Multiplexed I/O & Peripheral Pin MCLR#/VPP/RA5 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA2/AN2/VREF-: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC18F1320-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F1320-I/SO (SOIC-18-300mil) has a nominal body envelope of 7.50 × 11.55 mm, pitch e = 1.27 mm, and 18 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F1320-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F1320-I/SO (MICROCHIP, SOIC-18-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.50mm × 11.55mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (18/18)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RA0/AN0	I/O	Multiplexed I/O & Peripheral Pin RA0/AN0 (General)
2	RA1/AN1/LVDIN	I/O	Multiplexed I/O & Peripheral Pin RA1/AN1/LVDIN (General)
3	RA4/T0CKI	I/O	Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)
4	MCLR#/VPP/RA5	I/O	Multiplexed I/O & Peripheral Pin MCLR#/VPP/RA5 (General)
5	VSS	GND	Ground Reference Pin (VSS)
6	RA2/AN2/VREF-	Analog	Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
7	RA3/AN3/VREF+	Analog	Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
8	RB0/AN4/INT0	I/O	Multiplexed I/O & Peripheral Pin RB0/AN4/INT0 (General)
9	RB1/AN5/TX/CK/INT1	I/O	Multiplexed I/O & Peripheral Pin RB1/AN5/TX/CK/INT1 (General)
10	RB4/AN6/RX/DT/KBI0	I/O	Multiplexed I/O & Peripheral Pin RB4/AN6/RX/DT/KBI0 (General)
11	RB5/PGM/KBI1	I/O	Multiplexed I/O & Peripheral Pin RB5/PGM/KBI1 (General)
12	IO7	I/O	GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13	RB7/PGD/T1OSI/P1D/KBI3	I/O	Multiplexed I/O & Peripheral Pin RB7/PGD/T1OSI/P1D/KBI3 (General)
14	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
15	OSC2/CLKO/RA6	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO/RA6 (RTC/CLK)
16	OSC1/CLKI/RA7	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI/RA7 (RTC/CLK)
17	RB2/P1B/INT2	I/O	Multiplexed I/O & Peripheral Pin RB2/P1B/INT2 (General)
18	RB3/CCP1/P1A	I/O	Multiplexed I/O & Peripheral Pin RB3/CCP1/P1A (General)

PIN 1 RA0/AN0

I/O

Multiplexed I/O & Peripheral Pin RA0/AN0 (General)

Design note: Signal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC18F1320-I/SO (SOIC-18-300mil) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC18F1320-I/SO (SOIC-18-300mil) - 2. Standard Pinout (Top View)

True package pinout (18 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC18F1320-I/SO (SOIC-18-300mil) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC18F1320-I/SO (SOIC-18-300mil) - 4. Package Dimensions (D×E×A)

SOIC-18-300mil · 7.50×11.55mm · Pitch 1.27mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC18F1320-I/SO (SOIC-18-300mil) - 5. Recommended Land Pattern

IPC-7351B Footprint (18 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC18F1320-I/SO (SOIC-18-300mil) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for PIC18F1320

P2 · p02_fig01P2

Datasheet Page 2 (p02_fig01)

P96 · p96_fig011632×511px

FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE

P96 · p96_fig021700×643px

FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE

P110 · p110_fig011772×511px

• every falling edge • every rising edge • every 4th rising edge • every 16th rising edge

P110 · p110_fig01P110

Datasheet Page 110 (p110_fig01)

P111 · p111_fig011771×630px

FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

P123 · p123_fig011524×521px

FIGURE 15-12: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)

P123 · p123_fig021777×738px

FIGURE 15-13: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)

P280 · p280_fig01P280

Datasheet Page 280 (p280_fig01)

P1 · p01_fig01All Packages in PDF

18/20/28-Pin High-Performance, Enhanced Flash MCUs with 10-bit A/D

P2 · p02_fig01All Packages in PDF

28-Pin QFN

P2 · p02_fig02All Packages in PDF

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (PIC18F1320-I/SO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC18F1320-I/SO (SOIC-18-300mil) is a 18-pin standard electronic & interconnect component featuring a 11.55 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2.0V to 5.5V supply operation across -10°C to +70°C with integrated UART, ADC, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.0V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-10°C to +70°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

11.55 × 7.50 × 2.70 mm (A1=0.20 mm)

Package family: SOIC (SOIC-18-300mil)

Pin Count & Lead PitchN / e

18 Pins | Pitch e = 1.27 mm (50.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, ADC, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol18 auto-grouped pins

IPC-7351B Land Pattern18 pads · Pitch 1.27mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-18-300mil)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

11.55 × 7.50 mm

Height (A) & Pitch (e)IPC-7351B

A=2.70mm · e=1.27mm

Pad Size (W × L)Level B

0.60 × 1.90 mm

Pins / Total PadsTopology

18P / 18Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit SOIC-18-300mil	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F1320-I/SO (SOIC-18-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F1320-I/SO (SOIC-18-300mil)?

Manufactured by MICROCHIP, the PIC18F1320-I/SO is housed in a SOIC-18-300mil package with 18 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 2 (RA1/AN1/LVDIN: Multiplexed I/O & Peripheral Pin RA1/AN1/LVDIN (General)), 3 (RA4/T0CKI: Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)), 4 (MCLR#/VPP/RA5: Multiplexed I/O & Peripheral Pin MCLR#/VPP/RA5 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA2/AN2/VREF-: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F1320-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F1320-I/SO (SOIC-18-300mil) has a nominal body envelope of 7.50 × 11.55 mm, pitch e = 1.27 mm, and 18 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F1320-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F1320-I/SO (MICROCHIP, SOIC-18-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (18 pins) & PIC18F1320 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RA0/AN0	Digital_IO	Signal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
2	RA1/AN1/LVDIN	Digital_IO	Signal terminal RA1/AN1/LVDIN (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1/LVDIN. Supported peripheral buses: General.
3	RA4/T0CKI	Digital_IO	Signal terminal RA4/T0CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI. Supported peripheral buses: General.
4	MCLR#/VPP/RA5	Digital_IO	Signal terminal MCLR#/VPP/RA5 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP/RA5. Supported peripheral buses: General.
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	RA2/AN2/VREF-	Analog	Signal terminal RA2/AN2/VREF- (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
7	RA3/AN3/VREF+	Analog	Signal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
8	RB0/AN4/INT0	Digital_IO	Signal terminal RB0/AN4/INT0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/AN4/INT0. Supported peripheral buses: General.
9	RB1/AN5/TX/CK/INT1	Digital_IO	Signal terminal RB1/AN5/TX/CK/INT1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/AN5/TX/CK/INT1. Supported peripheral buses: General.
10	RB4/AN6/RX/DT/KBI0	Digital_IO	Signal terminal RB4/AN6/RX/DT/KBI0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/AN6/RX/DT/KBI0. Supported peripheral buses: General.
11	RB5/PGM/KBI1	Digital_IO	Signal terminal RB5/PGM/KBI1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/PGM/KBI1. Supported peripheral buses: General.
12	IO7	Digital_IO	GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13	RB7/PGD/T1OSI/P1D/KBI3	Digital_IO	Signal terminal RB7/PGD/T1OSI/P1D/KBI3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/PGD/T1OSI/P1D/KBI3. Supported peripheral buses: General.
14	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
15	OSC2/CLKO/RA6	Digital_IO	Signal terminal OSC2/CLKO/RA6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO/RA6. Supported peripheral buses: RTC/CLK.
16	OSC1/CLKI/RA7	Digital_IO	Signal terminal OSC1/CLKI/RA7 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKI/RA7. Supported peripheral buses: RTC/CLK.
17	RB2/P1B/INT2	Digital_IO	Signal terminal RB2/P1B/INT2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/P1B/INT2. Supported peripheral buses: General.
18	RB3/CCP1/P1A	Digital_IO	Signal terminal RB3/CCP1/P1A (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/CCP1/P1A. Supported peripheral buses: General.

4D Studio: PIC18F1320-I/SO Permalink: /part/C219556 MICROCHIP SOIC-18-300mil All Packages All Manufacturers