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CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) — Symbol, Footprint IPC-7351B & 3D STEP Model

CRT9007DECCD

MICROCHIPID: C20554273PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL · 40 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)1VA22VA103VA34VA115VA126VA47VA138VA59VA610VA711VLT12VS#13HS#14CCLK#15DRB#16VD717VD618VD519VD420VD340GND39VA938VA137VA836VA035CBLANK34CURS33ACK/TSC#32CSYNC#/LPSTB31SLD/SL030SLG#/SL129WBEN/SL2/CSY28DMAR/SL3/VBL27INT26RST#25CS#24VD023VD122VD221+5VGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940E=13.90mm · Pitch e=2.54mmD=50.26mm-22-20-18-16-14-12-10-8-6-4-2024681012141618202239373533312927252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27-29-31-33-35-37-39mm
3. 3D CAD MODEL
Package Body: 13.90mm × 50.26mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VA2I/OMultiplexed I/O & Peripheral Pin VA2 (General)
2VA10I/OMultiplexed I/O & Peripheral Pin VA10 (General)
3VA3I/OMultiplexed I/O & Peripheral Pin VA3 (General)
4VA11I/OMultiplexed I/O & Peripheral Pin VA11 (General)
5VA12I/OMultiplexed I/O & Peripheral Pin VA12 (General)
6VA4I/OMultiplexed I/O & Peripheral Pin VA4 (General)
7VA13I/OMultiplexed I/O & Peripheral Pin VA13 (General)
8VA5I/OMultiplexed I/O & Peripheral Pin VA5 (General)
9VA6I/OMultiplexed I/O & Peripheral Pin VA6 (General)
10VA7I/OMultiplexed I/O & Peripheral Pin VA7 (General)
11VLTI/OMultiplexed I/O & Peripheral Pin VLT (General)
12VS#I/OMultiplexed I/O & Peripheral Pin VS# (General)
13HS#I/OMultiplexed I/O & Peripheral Pin HS# (General)
14CCLK#I/OMultiplexed I/O & Peripheral Pin CCLK# (General)
15DRB#I/OMultiplexed I/O & Peripheral Pin DRB# (General)
16VD7I/OMultiplexed I/O & Peripheral Pin VD7 (General)
17VD6I/OMultiplexed I/O & Peripheral Pin VD6 (General)
18VD5I/OMultiplexed I/O & Peripheral Pin VD5 (General)
19VD4I/OMultiplexed I/O & Peripheral Pin VD4 (General)
20VD3I/OMultiplexed I/O & Peripheral Pin VD3 (General)
21+5VPowerPower Supply Input (+5V — 3.3V / 5.0V Standard Logic)
22VD2I/OMultiplexed I/O & Peripheral Pin VD2 (General)
23VD1I/OMultiplexed I/O & Peripheral Pin VD1 (General)
24VD0I/OMultiplexed I/O & Peripheral Pin VD0 (General)
25CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
26RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
27INTI/OMultiplexed I/O & Peripheral Pin INT (General)
28DMAR/SL3/VBLANKI/OMultiplexed I/O & Peripheral Pin DMAR/SL3/VBLANK (General)
29WBEN/SL2/CSYNC#I/OMultiplexed I/O & Peripheral Pin WBEN/SL2/CSYNC# (General)
30SLG#/SL1I/OMultiplexed I/O & Peripheral Pin SLG#/SL1 (General)
31SLD/SL0I/OMultiplexed I/O & Peripheral Pin SLD/SL0 (General)
32CSYNC#/LPSTBI/OMultiplexed I/O & Peripheral Pin CSYNC#/LPSTB (General)
33ACK/TSC#I/OMultiplexed I/O & Peripheral Pin ACK/TSC# (General)
34CURSI/OMultiplexed I/O & Peripheral Pin CURS (General)
35CBLANKI/OMultiplexed I/O & Peripheral Pin CBLANK (General)
36VA0I/OMultiplexed I/O & Peripheral Pin VA0 (General)
37VA8I/OMultiplexed I/O & Peripheral Pin VA8 (General)
38VA1I/OMultiplexed I/O & Peripheral Pin VA1 (General)
39VA9I/OMultiplexed I/O & Peripheral Pin VA9 (General)
40GNDGNDGround Reference Pin (GND)
PIN 1 VA2
I/O
Multiplexed I/O & Peripheral Pin VA2 (General)
Design note: Signal terminal VA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CRT9007DECCD (MICROCHIP · PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) - 2. Standard Pinout (Top View)
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) - 4. Package Dimensions (D×E×A)
PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL · 13.90×50.26mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) - 5. Recommended Land Pattern
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CRT9007
P1 · p01_fig011803×2302px
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) — STANDARD MICROSYSTEMS CRT9007A2* ——_—— CRT9OO7A” VP, A Cc” *PRELIMINARY FEATURES PIN CONFIGURATION Ci Fully Programmable Display Format Characters per Data Row (8-240) i, Data Rows per Frame (2-256) vaz1 D 40GNno Raster Scans per Data Row (
STANDARD MICROSYSTEMS CRT9007A2* ——_—— CRT9OO7A” VP, A Cc” *PRELIMINARY FEATURES PIN CONFIGURATION Ci Fully Programmable Display Format Characters per Data Row (8-240) i, Data Rows per Frame (2-256) vaz1 D 40GNno Raster Scans per Data Row (
P1 · p01_fig01P1
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig011803×2302px
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) — [commence cone] [— sanatranon —[arenomrnie | [—rorzoewr | sominesonnnow | [“Fenonewors | somcnesrae | [— rerio [mess enero] [eva ] [ser] [emare] (ee) =e [I ese eras : a a chon ssoumeune = : a = a eK. — DESCRIPTION OF PIN FUNCTIONS PROCESSOR
[commence cone] [— sanatranon —[arenomrnie | [—rorzoewr | sominesonnnow | [“Fenonewors | somcnesrae | [— rerio [mess enero] [eva ] [ser] [emare] (ee) =e [I ese eras : a a chon ssoumeune = : a = a eK. — DESCRIPTION OF PIN FUNCTIONS PROCESSOR
P20 · p20_fig011803×2302px
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) — ‘AC ELECTRICAL CHARACTERISTICS® T, = 0°C to + 70°C, Voc = 5.0V + 5% | ys Nite tna , ¥] sind Ce acca, SYMBOL PARAMETER [wn [ve | Max [uns [SS ihe | Clock: a S| ter Clock period 155 Teo ns CRT9007A2 All operation modes 200 TBD ns CRT9O07A1 te
‘AC ELECTRICAL CHARACTERISTICS® T, = 0°C to + 70°C, Voc = 5.0V + 5% | ys Nite tna , ¥] sind Ce acca, SYMBOL PARAMETER [wn [ve | Max [uns [SS ihe | Clock: a S| ter Clock period 155 Teo ns CRT9007A2 All operation modes 200 TBD ns CRT9O07A1 te
P21 · p21_fig011803×2302px
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) — ow femme tons ey oR tee: tos: UT. WBEN ORB Toe sive a | _ SYNC. OMAR, ‘CBLANK og #8, V8 = vore { Y x Baur Noe: tom: > xs [> é Tas 5 ao a, 3 Ta +5V curs [ 3900 cy __ ‘e ToCCIK NT Input —_ 74804 or equivalent : : FIGURE 25: RECOMMENDED CCLK F
ow femme tons ey oR tee: tos: UT. WBEN ORB Toe sive a | _ SYNC. OMAR, ‘CBLANK og #8, V8 = vore { Y x Baur Noe: tom: > xs [> é Tas 5 ao a, 3 Ta +5V curs [ 3900 cy __ ‘e ToCCIK NT Input —_ 74804 or equivalent : : FIGURE 25: RECOMMENDED CCLK F
P22 · p22_fig011803×2302px
CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) — neassren ADORESS DECODE err oeWTON vias epsterTyoe VAS _VAt_VA3_VA2 VAI AO 0708 O5—t_—os oe wwe [afe]ele [es] faa Samcerontacti Ss] w wine [ofol}olo{o]s || ns GraeacTeRGPEROATAROW | 59 ™ we fotefetets fo] we [efefetep te] ° wwe [etetet rte
neassren ADORESS DECODE err oeWTON vias epsterTyoe VAS _VAt_VA3_VA2 VAI AO 0708 O5—t_—os oe wwe [afe]ele [es] faa Samcerontacti Ss] w wine [ofol}olo{o]s || ns GraeacTeRGPEROATAROW | 59 ™ we fotefetets fo] we [efefetep te] ° wwe [etetet rte

Technical Specifications & Part Details (CRT9007DECCD)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) is a 40-pin standard electronic & interconnect component featuring a 50.26 × 13.90 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
50.26 × 13.90 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol40 auto-grouped pins
OK
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
50.26 × 13.90 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)?

Manufactured by MICROCHIP, the CRT9007DECCD is housed in a PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL package with 40 pins and a 2.54 mm lead pitch. Key pins include: 1 (VA2: Multiplexed I/O & Peripheral Pin VA2 (General)), 2 (VA10: Multiplexed I/O & Peripheral Pin VA10 (General)), 3 (VA3: Multiplexed I/O & Peripheral Pin VA3 (General)), 4 (VA11: Multiplexed I/O & Peripheral Pin VA11 (General)), 5 (VA12: Multiplexed I/O & Peripheral Pin VA12 (General)), 6 (VA4: Multiplexed I/O & Peripheral Pin VA4 (General)).

What are the IPC-7351B PCB Footprint dimensions for CRT9007DECCD?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CRT9007DECCD (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) has a nominal body envelope of 13.90 × 50.26 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CRT9007DECCD?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CRT9007DECCD (MICROCHIP, PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & CRT9007 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VA2Digital_IOSignal terminal VA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA2. Supported peripheral buses: General.
2VA10Digital_IOSignal terminal VA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA10. Supported peripheral buses: General.
3VA3Digital_IOSignal terminal VA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA3. Supported peripheral buses: General.
4VA11Digital_IOSignal terminal VA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA11. Supported peripheral buses: General.
5VA12Digital_IOSignal terminal VA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA12. Supported peripheral buses: General.
6VA4Digital_IOSignal terminal VA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA4. Supported peripheral buses: General.
7VA13Digital_IOSignal terminal VA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA13. Supported peripheral buses: General.
8VA5Digital_IOSignal terminal VA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA5. Supported peripheral buses: General.
9VA6Digital_IOSignal terminal VA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA6. Supported peripheral buses: General.
10VA7Digital_IOSignal terminal VA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA7. Supported peripheral buses: General.
11VLTDigital_IOSignal terminal VLT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VLT. Supported peripheral buses: General.
12VS#Digital_IOSignal terminal VS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VS#. Supported peripheral buses: General.
13HS#Digital_IOSignal terminal HS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HS#. Supported peripheral buses: General.
14CCLK#Digital_IOSignal terminal CCLK# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCLK#. Supported peripheral buses: General.
15DRB#Digital_IOSignal terminal DRB# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRB#. Supported peripheral buses: General.
16VD7Digital_IOSignal terminal VD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD7. Supported peripheral buses: General.
17VD6Digital_IOSignal terminal VD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD6. Supported peripheral buses: General.
18VD5Digital_IOSignal terminal VD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD5. Supported peripheral buses: General.
19VD4Digital_IOSignal terminal VD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD4. Supported peripheral buses: General.
20VD3Digital_IOSignal terminal VD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD3. Supported peripheral buses: General.
21+5VPower_InPrimary positive power supply input (+5V) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22VD2Digital_IOSignal terminal VD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD2. Supported peripheral buses: General.
23VD1Digital_IOSignal terminal VD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD1. Supported peripheral buses: General.
24VD0Digital_IOSignal terminal VD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD0. Supported peripheral buses: General.
25CS#Digital_IOSignal terminal CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
26RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
27INTDigital_IOSignal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
28DMAR/SL3/VBLANKDigital_IOSignal terminal DMAR/SL3/VBLANK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DMAR/SL3/VBLANK. Supported peripheral buses: General.
29WBEN/SL2/CSYNC#Digital_IOSignal terminal WBEN/SL2/CSYNC# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WBEN/SL2/CSYNC#. Supported peripheral buses: General.
30SLG#/SL1Digital_IOSignal terminal SLG#/SL1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLG#/SL1. Supported peripheral buses: General.
31SLD/SL0Digital_IOSignal terminal SLD/SL0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLD/SL0. Supported peripheral buses: General.
32CSYNC#/LPSTBDigital_IOSignal terminal CSYNC#/LPSTB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CSYNC#/LPSTB. Supported peripheral buses: General.
33ACK/TSC#Digital_IOSignal terminal ACK/TSC# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACK/TSC#. Supported peripheral buses: General.
34CURSDigital_IOSignal terminal CURS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CURS. Supported peripheral buses: General.
35CBLANKDigital_IOSignal terminal CBLANK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBLANK. Supported peripheral buses: General.
36VA0Digital_IOSignal terminal VA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA0. Supported peripheral buses: General.
37VA8Digital_IOSignal terminal VA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA8. Supported peripheral buses: General.
38VA1Digital_IOSignal terminal VA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA1. Supported peripheral buses: General.
39VA9Digital_IOSignal terminal VA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA9. Supported peripheral buses: General.
40GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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