Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-28-EP(6x6) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — PIC24FJ128GB202-I/MM (QFN-28-EP(6x6))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of PIC24FJ128GB202-I/MM (QFN-28-EP(6x6))?
Manufactured by MICROCHIP, the PIC24FJ128GB202-I/MM is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.0V to 3.6V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (AN11/RP17/CN9/RC1: Multiplexed I/O & Peripheral Pin AN11/RP17/CN9/RC1 (General)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (VDD: Power Supply Input (VDD — 2.0V to 3.6V)).
What are the IPC-7351B PCB Footprint dimensions for PIC24FJ128GB202-I/MM?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24FJ128GB202-I/MM (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24FJ128GB202-I/MM?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24FJ128GB202-I/MM (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (29 pins) & PIC24FJ128GB Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO1 | Digital_IO | General Purpose Digital I/O Pin IO1 |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | AN11/RP17/CN9/RC1 | Digital_IO | Signal terminal AN11/RP17/CN9/RC1 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: AN11/RP17/CN9/RC1. Supported peripheral buses: General. |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V). |
| 7 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 8 | IO0 | Digital_IO | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | IO4 | Digital_IO | GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3 |
| 10 | TDO/PMA8/CN34/RA8 | Digital_IO | Signal terminal TDO/PMA8/CN34/RA8 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: TDO/PMA8/CN34/RA8. Supported peripheral buses: General. |
| 11 | SOSCI/CN1/RPI4/RB4 | Digital_IO | Signal terminal SOSCI/CN1/RPI4/RB4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: SOSCI/CN1/RPI4/RB4. Supported peripheral buses: General. |
| 12 | SOSCO/SCLKI/CN0/RA4 | Digital_IO | Signal terminal SOSCO/SCLKI/CN0/RA4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: SOSCO/SCLKI/CN0/RA4. Supported peripheral buses: SPI, I2C. |
| 13 | TDI/PMA9/CN35/RA9 | Digital_IO | Signal terminal TDI/PMA9/CN35/RA9 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: TDI/PMA9/CN35/RA9. Supported peripheral buses: General. |
| 14 | RP19/PMBE0/CN28/RC3 | Digital_IO | Signal terminal RP19/PMBE0/CN28/RC3 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RP19/PMBE0/CN28/RC3. Supported peripheral buses: RTC/CLK. |
| 15 | RP20/PMA4/CN25/RC4 | Digital_IO | Signal terminal RP20/PMA4/CN25/RC4 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RP20/PMA4/CN25/RC4. Supported peripheral buses: General. |
| 16 | RP21/PMA3/CN26/RC5 | Digital_IO | Signal terminal RP21/PMA3/CN26/RC5 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: RP21/PMA3/CN26/RC5. Supported peripheral buses: General. |
| 17 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 18 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V). |
| 19 | CN27/USBID/RB5 | Digital_IO | Signal terminal CN27/USBID/RB5 (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: CN27/USBID/RB5. Supported peripheral buses: USB. |
| 20 | PMD6/CN24/VBUS/RB6 | Power_In | Primary positive power supply input (PMD6/CN24/VBUS/RB6) operating in the 2.0V to 3.6V domain (Max rating: 3.6V). |
| 21 | IO10 | Digital_IO | GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0 |
| 22 | IO11 | Digital_IO | GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID |
| 23 | IO12 | Digital_IO | GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK |
| 24 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 25 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.0V to 3.6V domain (Max rating: 3.6V). |
| 26 | MCLR# | Digital_IO | Signal terminal MCLR# (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General. |
| 27 | IO47 | Digital_IO | GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF |
| 28 | IO33 | Digital_IO | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |