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CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CEC1736-S0-I/2HW-PROTO

MICROCHIPID: C17395727VFBGA-64(5.5x5.5) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5))A2GPIO143/I2C0A3IOA3A4IOA4A5VSSA6IOA6A7GPIO022/QSPIA8GPIO023/QSPIA9IOA9B1IOB1B2IOB2B3IOB3B4IOB4B5VSSB6GPIO253/TST_B7IOB7B8VTR1B9IOB9B10GPIO204/QSPIC1GPIO140/I2C0C2GPIO046/SP1_C9GPIO202/QSPIC10GPIO250/SPI0D1VR_CAPD2GPIO132/I2C0D4VTR_ANALOGD7VTR_REGD9VSSD10IOD10E1IOE1E2IOE2E9IOE9E10GPIO203/QSPIK9VTR_PLLK8IOK8K7GPIO013/SP1_K6IOK6K5IOK5K4VR_CAPK3GPIO047/SP1_K2GPIO027/ALT_J10GPIO156/LED0J9IOJ9J8GPIO170[JTAGJ7GPIO127/SP1_J6IOJ6J5GPIO053/PWM0J4GPIO057/VCC_J3GPIO012(EXTRJ2IOJ2J1VSSH10nRESET_INH9JTAG_RST#H2GPIO050/ICT0H1GPIO063/SP1_G10GPIO157/LED1G9GPIO020/QSPIG7VSSG4nRESET_ING2GPIO004/I2C0G1JTAG RST#_F10VSSF9IOF9F2GPIO015/ICT1F1VTR_PLLGrid Pitch = 2.54mm (IEEE-315)-20.3-15.2-10.2-5.105.110.215.220.345.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
B1C1D1E1F1G1H1J1A2B2C2D2E2F2G2H2J2K2A3B3J3K3A4B4D4G4J4K4A5B5J5K5A6B6J6K6A7B7D7G7J7K7A8B8J8K8A9B9C9D9E9F9G9H9J9K9B10C10D10E10F10G10H10J10E=5.50mm · Pitch e=0.50mmD=5.50mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.50mm × 5.50mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2GPIO143/I2C04_SDAI/OMultiplexed I/O & Peripheral Pin GPIO143/I2C04_SDA (I2C)
A3IOA3I/OGeneral Purpose Digital I/O Pin IOA3
A4IOA4I/OGeneral Purpose Digital I/O Pin IOA4
A5VSSGNDGround Reference Pin (VSS)
A6IOA6I/OGeneral Purpose Digital I/O Pin IOA6
A7GPIO022/QSPI0_IN_IO1I/OMultiplexed I/O & Peripheral Pin GPIO022/QSPI0_IN_IO1 (SPI)
A8GPIO023/QSPI0_IN_IO0I/OMultiplexed I/O & Peripheral Pin GPIO023/QSPI0_IN_IO0 (SPI)
A9IOA9I/OGeneral Purpose Digital I/O Pin IOA9
B1IOB1I/OGeneral Purpose Digital I/O Pin IOB1
B2IOB2I/OGeneral Purpose Digital I/O Pin IOB2
B3IOB3I/OGeneral Purpose Digital I/O Pin IOB3
B4IOB4I/OGeneral Purpose Digital I/O Pin IOB4
B5VSSGNDGround Reference Pin (VSS)
B6GPIO253/TST_CLK_OUTI/OMultiplexed I/O & Peripheral Pin GPIO253/TST_CLK_OUT (General)
B7IOB7I/OGeneral Purpose Digital I/O Pin IOB7
B8VTR1I/OMultiplexed I/O & Peripheral Pin VTR1 (General)
B9IOB9I/OGeneral Purpose Digital I/O Pin IOB9
B10GPIO204/QSPI0_IN_CLKI/OMultiplexed I/O & Peripheral Pin GPIO204/QSPI0_IN_CLK (SPI)
C1GPIO140/I2C06_SCLI/OMultiplexed I/O & Peripheral Pin GPIO140/I2C06_SCL (I2C)
C2GPIO046/SP1_ALT_CS#I/OMultiplexed I/O & Peripheral Pin GPIO046/SP1_ALT_CS# (General)
C9GPIO202/QSPI0_IN_IO2I/OMultiplexed I/O & Peripheral Pin GPIO202/QSPI0_IN_IO2 (SPI)
C10GPIO250/SPI0PER_CS#I/OMultiplexed I/O & Peripheral Pin GPIO250/SPI0PER_CS# (SPI)
D1VR_CAPI/OMultiplexed I/O & Peripheral Pin VR_CAP (General)
D2GPIO132/I2C06_SDAI/OMultiplexed I/O & Peripheral Pin GPIO132/I2C06_SDA (I2C)
D4VTR_ANALOGI/OMultiplexed I/O & Peripheral Pin VTR_ANALOG (General)
D7VTR_REGI/OMultiplexed I/O & Peripheral Pin VTR_REG (General)
D9VSSGNDGround Reference Pin (VSS)
D10IOD10I/OGeneral Purpose Digital I/O Pin IOD10
E1IOE1I/OGeneral Purpose Digital I/O Pin IOE1
E2IOE2I/OGeneral Purpose Digital I/O Pin IOE2
E9IOE9I/OGeneral Purpose Digital I/O Pin IOE9
E10GPIO203/QSPI0_IN_IO3I/OMultiplexed I/O & Peripheral Pin GPIO203/QSPI0_IN_IO3 (SPI)
F1VTR_PLLI/OMultiplexed I/O & Peripheral Pin VTR_PLL (General)
F2GPIO015/ICT10[BSTRAP]I/OMultiplexed I/O & Peripheral Pin GPIO015/ICT10[BSTRAP] (General)
F9IOF9I/OGeneral Purpose Digital I/O Pin IOF9
F10VSSGNDGround Reference Pin (VSS)
G1JTAG RST#_I/OMultiplexed I/O & Peripheral Pin JTAG RST#_ (SWD/JTAG)
G2GPIO004/I2C00_SCLI/OMultiplexed I/O & Peripheral Pin GPIO004/I2C00_SCL (I2C)
G4nRESET_INISystem Enable & Hardware Reset (nRESET_IN)
G7VSSGNDGround Reference Pin (VSS)
G9GPIO020/QSPI0_IN_CS0#I/OMultiplexed I/O & Peripheral Pin GPIO020/QSPI0_IN_CS0# (SPI)
G10GPIO157/LED1I/OMultiplexed I/O & Peripheral Pin GPIO157/LED1 (General)
H1GPIO063/SP1_ALT_CLKI/OMultiplexed I/O & Peripheral Pin GPIO063/SP1_ALT_CLK (General)
H2GPIO050/ICT0I/OMultiplexed I/O & Peripheral Pin GPIO050/ICT0 (General)
H9JTAG_RST#I/OMultiplexed I/O & Peripheral Pin JTAG_RST# (SWD/JTAG)
H10nRESET_INISystem Enable & Hardware Reset (nRESET_IN)
J1VSSGNDGround Reference Pin (VSS)
J2IOJ2I/OGeneral Purpose Digital I/O Pin IOJ2
J3GPIO012(EXTRST#)I/OMultiplexed I/O & Peripheral Pin GPIO012(EXTRST#) (General)
J4GPIO057/VCC_PWRGDPowerPower Supply Input (GPIO057/VCC_PWRGD — 3.3V / 5.0V Standard Logic)
J5GPIO053/PWM0I/OMultiplexed I/O & Peripheral Pin GPIO053/PWM0 (PWM)
J6IOJ6I/OGeneral Purpose Digital I/O Pin IOJ6
J7GPIO127/SP1_ALT_IO2I/OMultiplexed I/O & Peripheral Pin GPIO127/SP1_ALT_IO2 (General)
J8GPIO170[JTAG_STRAP]I/OMultiplexed I/O & Peripheral Pin GPIO170[JTAG_STRAP] (SWD/JTAG)
J9IOJ9I/OGeneral Purpose Digital I/O Pin IOJ9
J10GPIO156/LED0I/OMultiplexed I/O & Peripheral Pin GPIO156/LED0 (General)
K2GPIO027/ALT_TFDP_CLKI/OMultiplexed I/O & Peripheral Pin GPIO027/ALT_TFDP_CLK (General)
K3GPIO047/SP1_ALT_IO1I/OMultiplexed I/O & Peripheral Pin GPIO047/SP1_ALT_IO1 (General)
K4VR_CAPI/OMultiplexed I/O & Peripheral Pin VR_CAP (General)
K5IOK5I/OGeneral Purpose Digital I/O Pin IOK5
K6IOK6I/OGeneral Purpose Digital I/O Pin IOK6
K7GPIO013/SP1_ALT_IO3I/OMultiplexed I/O & Peripheral Pin GPIO013/SP1_ALT_IO3 (General)
K8IOK8I/OGeneral Purpose Digital I/O Pin IOK8
K9VTR_PLLI/OMultiplexed I/O & Peripheral Pin VTR_PLL (General)
PIN A2 GPIO143/I2C04_SDA
I/O
Multiplexed I/O & Peripheral Pin GPIO143/I2C04_SDA (I2C)
Design note: Signal terminal GPIO143/I2C04_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO143/I2C04_SDA. Supported peripheral buses: I2C.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CEC1736-S0-I/2HW-PROTO (MICROCHIP · VFBGA-64(5.5x5.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) - 4. Package Dimensions (D×E×A)
VFBGA-64(5.5x5.5) · 5.50×5.50mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CEC1736
P1 · p01_fig01377×200px
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) — Real Time Platform Root of Trust Controllers
Real Time Platform Root of Trust Controllers
P44 · p44_fig011777×2084px
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) — FIGURE 2-1: 2HW Package Dimensions, Sheet 1
FIGURE 2-1: 2HW Package Dimensions, Sheet 1
P47 · p47_fig011595×1858px
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) — FIGURE 2-4: 2ZW Package Dimensions, Sheet 1
FIGURE 2-4: 2ZW Package Dimensions, Sheet 1
P47 · p47_fig01P47
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) — Datasheet Page 47 (p47_fig01)
Datasheet Page 47 (p47_fig01)
P48 · p48_fig011596×962px
CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) — FIGURE 2-5: 2ZW Package Dimensions, Sheet 2
FIGURE 2-5: 2ZW Package Dimensions, Sheet 2

Technical Specifications & Part Details (CEC1736-S0-I/2HW-PROTO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) is a 64-pin standard electronic & interconnect component featuring a 5.50 × 5.50 × 0.80 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, UART, SPI, I2C, PWM, JTAG / SWD, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
96 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.50 × 5.50 × 0.80 mm (A1=0.22 mm)
Package family: BGA (VFBGA-64(5.5x5.5))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, UART, SPI, I2C, PWM, JTAG / SWD, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VFBGA-64(5.5x5.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.50 × 5.50 mm
Height (A) & Pitch (e)IPC-7351B
A=0.80mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VFBGA-64(5.5x5.5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5))?

Manufactured by MICROCHIP, the CEC1736-S0-I/2HW-PROTO is housed in a VFBGA-64(5.5x5.5) package with 64 pins and a 0.50 mm lead pitch. Key pins include: A2 (GPIO143/I2C04_SDA: Multiplexed I/O & Peripheral Pin GPIO143/I2C04_SDA (I2C)), A3 (IOA3: General Purpose Digital I/O Pin IOA3), A4 (IOA4: General Purpose Digital I/O Pin IOA4), A5 (VSS: Ground Reference Pin (VSS)), A6 (IOA6: General Purpose Digital I/O Pin IOA6), A7 (GPIO022/QSPI0_IN_IO1: Multiplexed I/O & Peripheral Pin GPIO022/QSPI0_IN_IO1 (SPI)).

What are the IPC-7351B PCB Footprint dimensions for CEC1736-S0-I/2HW-PROTO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CEC1736-S0-I/2HW-PROTO (VFBGA-64(5.5x5.5)) has a nominal body envelope of 5.50 × 5.50 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CEC1736-S0-I/2HW-PROTO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CEC1736-S0-I/2HW-PROTO (MICROCHIP, VFBGA-64(5.5x5.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CEC1736 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2GPIO143/I2C04_SDADigital_IOSignal terminal GPIO143/I2C04_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO143/I2C04_SDA. Supported peripheral buses: I2C.
A3IOA3Digital_IOGeneral Purpose Digital I/O Pin IOA3
A4IOA4Digital_IOGeneral Purpose Digital I/O Pin IOA4
A5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A6IOA6Digital_IOGeneral Purpose Digital I/O Pin IOA6
A7GPIO022/QSPI0_IN_IO1Digital_IOSignal terminal GPIO022/QSPI0_IN_IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO022/QSPI0_IN_IO1. Supported peripheral buses: SPI.
A8GPIO023/QSPI0_IN_IO0Digital_IOSignal terminal GPIO023/QSPI0_IN_IO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO023/QSPI0_IN_IO0. Supported peripheral buses: SPI.
A9IOA9Digital_IOGeneral Purpose Digital I/O Pin IOA9
B1IOB1Digital_IOGeneral Purpose Digital I/O Pin IOB1
B2IOB2Digital_IOGeneral Purpose Digital I/O Pin IOB2
B3IOB3Digital_IOGeneral Purpose Digital I/O Pin IOB3
B4IOB4Digital_IOGeneral Purpose Digital I/O Pin IOB4
B5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B6GPIO253/TST_CLK_OUTDigital_IOSignal terminal GPIO253/TST_CLK_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO253/TST_CLK_OUT. Supported peripheral buses: General.
B7IOB7Digital_IOGeneral Purpose Digital I/O Pin IOB7
B8VTR1Digital_IOSignal terminal VTR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR1. Supported peripheral buses: General.
B9IOB9Digital_IOGeneral Purpose Digital I/O Pin IOB9
B10GPIO204/QSPI0_IN_CLKDigital_IOSignal terminal GPIO204/QSPI0_IN_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO204/QSPI0_IN_CLK. Supported peripheral buses: SPI.
C1GPIO140/I2C06_SCLDigital_IOSignal terminal GPIO140/I2C06_SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO140/I2C06_SCL. Supported peripheral buses: I2C.
C2GPIO046/SP1_ALT_CS#Digital_IOSignal terminal GPIO046/SP1_ALT_CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO046/SP1_ALT_CS#. Supported peripheral buses: General.
C9GPIO202/QSPI0_IN_IO2Digital_IOSignal terminal GPIO202/QSPI0_IN_IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO202/QSPI0_IN_IO2. Supported peripheral buses: SPI.
C10GPIO250/SPI0PER_CS#Digital_IOSignal terminal GPIO250/SPI0PER_CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO250/SPI0PER_CS#. Supported peripheral buses: SPI.
D1VR_CAPDigital_IOSignal terminal VR_CAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VR_CAP. Supported peripheral buses: General.
D2GPIO132/I2C06_SDADigital_IOSignal terminal GPIO132/I2C06_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO132/I2C06_SDA. Supported peripheral buses: I2C.
D4VTR_ANALOGDigital_IOSignal terminal VTR_ANALOG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR_ANALOG. Supported peripheral buses: General.
D7VTR_REGDigital_IOSignal terminal VTR_REG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR_REG. Supported peripheral buses: General.
D9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D10IOD10Digital_IOGeneral Purpose Digital I/O Pin IOD10
E1IOE1Digital_IOGeneral Purpose Digital I/O Pin IOE1
E2IOE2Digital_IOGeneral Purpose Digital I/O Pin IOE2
E9IOE9Digital_IOGeneral Purpose Digital I/O Pin IOE9
E10GPIO203/QSPI0_IN_IO3Digital_IOSignal terminal GPIO203/QSPI0_IN_IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO203/QSPI0_IN_IO3. Supported peripheral buses: SPI.
F1VTR_PLLDigital_IOSignal terminal VTR_PLL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR_PLL. Supported peripheral buses: General.
F2GPIO015/ICT10[BSTRAP]Digital_IOSignal terminal GPIO015/ICT10[BSTRAP] (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO015/ICT10[BSTRAP]. Supported peripheral buses: General.
F9IOF9Digital_IOGeneral Purpose Digital I/O Pin IOF9
F10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G1JTAG RST#_Digital_IOSignal terminal JTAG RST#_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: JTAG RST#_. Supported peripheral buses: SWD/JTAG.
G2GPIO004/I2C00_SCLDigital_IOSignal terminal GPIO004/I2C00_SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO004/I2C00_SCL. Supported peripheral buses: I2C.
G4nRESET_INDigital_IOActive-low hardware reset terminal (nRESET_IN): pulling this pin Low resets the processor core and peripherals.
G7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G9GPIO020/QSPI0_IN_CS0#Digital_IOSignal terminal GPIO020/QSPI0_IN_CS0# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO020/QSPI0_IN_CS0#. Supported peripheral buses: SPI.
G10GPIO157/LED1Digital_IOSignal terminal GPIO157/LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO157/LED1. Supported peripheral buses: General.
H1GPIO063/SP1_ALT_CLKDigital_IOSignal terminal GPIO063/SP1_ALT_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO063/SP1_ALT_CLK. Supported peripheral buses: General.
H2GPIO050/ICT0Digital_IOSignal terminal GPIO050/ICT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO050/ICT0. Supported peripheral buses: General.
H9JTAG_RST#Digital_IOSignal terminal JTAG_RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: JTAG_RST#. Supported peripheral buses: SWD/JTAG.
H10nRESET_INDigital_IOActive-low hardware reset terminal (nRESET_IN): pulling this pin Low resets the processor core and peripherals.
J1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
J2IOJ2Digital_IOGeneral Purpose Digital I/O Pin IOJ2
J3GPIO012(EXTRST#)Digital_IOSignal terminal GPIO012(EXTRST#) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO012(EXTRST#). Supported peripheral buses: General.
J4GPIO057/VCC_PWRGDPower_InPrimary positive power supply input (GPIO057/VCC_PWRGD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
J5GPIO053/PWM0Digital_IOSignal terminal GPIO053/PWM0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO053/PWM0. Supported peripheral buses: PWM.
J6IOJ6Digital_IOGeneral Purpose Digital I/O Pin IOJ6
J7GPIO127/SP1_ALT_IO2Digital_IOSignal terminal GPIO127/SP1_ALT_IO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO127/SP1_ALT_IO2. Supported peripheral buses: General.
J8GPIO170[JTAG_STRAP]Digital_IOSignal terminal GPIO170[JTAG_STRAP] (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO170[JTAG_STRAP]. Supported peripheral buses: SWD/JTAG.
J9IOJ9Digital_IOGeneral Purpose Digital I/O Pin IOJ9
J10GPIO156/LED0Digital_IOSignal terminal GPIO156/LED0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO156/LED0. Supported peripheral buses: General.
K2GPIO027/ALT_TFDP_CLKDigital_IOSignal terminal GPIO027/ALT_TFDP_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO027/ALT_TFDP_CLK. Supported peripheral buses: General.
K3GPIO047/SP1_ALT_IO1Digital_IOSignal terminal GPIO047/SP1_ALT_IO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO047/SP1_ALT_IO1. Supported peripheral buses: General.
K4VR_CAPDigital_IOSignal terminal VR_CAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VR_CAP. Supported peripheral buses: General.
K5IOK5Digital_IOGeneral Purpose Digital I/O Pin IOK5
K6IOK6Digital_IOGeneral Purpose Digital I/O Pin IOK6
K7GPIO013/SP1_ALT_IO3Digital_IOSignal terminal GPIO013/SP1_ALT_IO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO013/SP1_ALT_IO3. Supported peripheral buses: General.
K8IOK8Digital_IOGeneral Purpose Digital I/O Pin IOK8
K9VTR_PLLDigital_IOSignal terminal VTR_PLL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VTR_PLL. Supported peripheral buses: General.
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