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ATWILC1000B-UU-T (WLCSP-55) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATWILC1000B-UU-T

MICROCHIPID: C1558351WLCSP-55 · 55 Pins · Pitch 0.35mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATWILC1000B-UU-T (WLCSP-55)A1GPIO6A2I2C_SCLA3RESETNA4XO_NA5GND_SXDIGA6VDD_SXDIGA7VDDIO_AB1GPIO16B2GPIO5B3I2C_SDAB4XO_PB5GND_IOB6TP_NB7VDD_RFRX_B8NCC1VDDCC2GPIO15C3GPIO17C4GPIO18C5GPIO13C6TP_PC7GND_RFRX_D1VDDIOD2TEST_MODED3GPIO4D7VDD_BATTPA_D8GND_BATTPPA_E1VSSH8VDD_AMSH7GPIO11H6VDDCH5VDDIOH4VSSH3SD CMD/_ SPIH2VBATT_BUCKH1VSWG8TX_NG7SDIO_SPICFG_G6GPIO12G5SD DAT2/_ SPG4SD DAT1/_ SPG3SD DAT0/_ SPG2SD_CLKG1GND_BUCKF8TX_PF7GND_AMSF6GPIO0/ HOST_F5GPIO2/IRQNF4SD_DAT3F3VREG_BUCKF2CHIP_ENF1GND_BIASE7GND_BATTPA_E3GPIO3E2GPIO1/RTC_CLGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.840.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6mm
2. 2D FOOTPRINT
D3D2D7D1D8E1E7E2E3C1C7C2C6C3C5C4B8B1B7B2B6B3B5B4A1A7A2A6A3A5A4F4F5F3F6F2F7F1F8G4G5G3G6G2G7G1G8H4H5H3H6H2H7H1H8E=3.20mm · Pitch e=0.35mmD=3.20mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.20mm × 3.20mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (55/55)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (UART, SPI)
A2I2C_SCLI/OMultiplexed I/O & Peripheral Pin I2C_SCL (I2C)
A3RESETNISystem Enable & Hardware Reset (RESETN)
A4XO_NI/OMultiplexed I/O & Peripheral Pin XO_N (RTC/CLK)
A5GND_SXDIGGNDGround Reference Pin (GND_SXDIG)
A6VDD_SXDIGPowerPower Supply Input (VDD_SXDIG — 3.3V / 5.0V Standard Logic)
A7VDDIO_APowerPower Supply Input (VDDIO_A — 3.3V / 5.0V Standard Logic)
B1GPIO16I/OMultiplexed I/O & Peripheral Pin GPIO16 (General)
B2GPIO5I/OMultiplexed I/O & Peripheral Pin GPIO5 (UART, SPI)
B3I2C_SDAI/OMultiplexed I/O & Peripheral Pin I2C_SDA (I2C)
B4XO_PI/OMultiplexed I/O & Peripheral Pin XO_P (RTC/CLK)
B5GND_IOGNDGround Reference Pin (GND_IO)
B6TP_NI/OMultiplexed I/O & Peripheral Pin TP_N (General)
B7VDD_RFRX_PowerPower Supply Input (VDD_RFRX_ — 3.3V / 5.0V Standard Logic)
B8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
C1VDDCPowerPower Supply Input (VDDC — 3.3V / 5.0V Standard Logic)
C2GPIO15I/OMultiplexed I/O & Peripheral Pin GPIO15 (General)
C3GPIO17I/OMultiplexed I/O & Peripheral Pin GPIO17 (General)
C4GPIO18I/OMultiplexed I/O & Peripheral Pin GPIO18 (General)
C5GPIO13I/OMultiplexed I/O & Peripheral Pin GPIO13 (General)
C6TP_PI/OMultiplexed I/O & Peripheral Pin TP_P (General)
C7GND_RFRX_GNDGround Reference Pin (GND_RFRX_)
D1VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
D2TEST_MODEI/OMultiplexed I/O & Peripheral Pin TEST_MODE (General)
D3GPIO4I/OMultiplexed I/O & Peripheral Pin GPIO4 (SPI)
D7VDD_BATTPA_PowerPower Supply Input (VDD_BATTPA_ — 3.3V / 5.0V Standard Logic)
D8GND_BATTPPA_GNDGround Reference Pin (GND_BATTPPA_)
E1VSSGNDGround Reference Pin (VSS)
E2GPIO1/RTC_CLKI/OMultiplexed I/O & Peripheral Pin GPIO1/RTC_CLK (RTC/CLK)
E3GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (SPI)
E7GND_BATTPA_GNDGround Reference Pin (GND_BATTPA_)
F1GND_BIASGNDGround Reference Pin (GND_BIAS)
F2CHIP_ENI/OMultiplexed I/O & Peripheral Pin CHIP_EN (General)
F3VREG_BUCKPowerPower Supply Input (VREG_BUCK — 3.3V / 5.0V Standard Logic)
F4SD_DAT3I/OMultiplexed I/O & Peripheral Pin SD_DAT3 (General)
F5GPIO2/IRQNI/OMultiplexed I/O & Peripheral Pin GPIO2/IRQN (General)
F6GPIO0/ HOST_WAKEI/OMultiplexed I/O & Peripheral Pin GPIO0/ HOST_WAKE (General)
F7GND_AMSGNDGround Reference Pin (GND_AMS)
F8TX_PI/OMultiplexed I/O & Peripheral Pin TX_P (General)
G1GND_BUCKGNDGround Reference Pin (GND_BUCK)
G2SD_CLKI/OMultiplexed I/O & Peripheral Pin SD_CLK (General)
G3SD DAT0/_ SPI_TXDI/OMultiplexed I/O & Peripheral Pin SD DAT0/_ SPI_TXD (UART, SPI)
G4SD DAT1/_ SPI_SSNI/OMultiplexed I/O & Peripheral Pin SD DAT1/_ SPI_SSN (SPI)
G5SD DAT2/_ SPI_RXDI/OMultiplexed I/O & Peripheral Pin SD DAT2/_ SPI_RXD (UART, SPI)
G6GPIO12I/OMultiplexed I/O & Peripheral Pin GPIO12 (General)
G7SDIO_SPICFG_I/OMultiplexed I/O & Peripheral Pin SDIO_SPICFG_ (SPI)
G8TX_NI/OMultiplexed I/O & Peripheral Pin TX_N (General)
H1VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
H2VBATT_BUCKPowerPower Supply Input (VBATT_BUCK — 3.3V / 5.0V Standard Logic)
H3SD CMD/_ SPI_SCKI/OMultiplexed I/O & Peripheral Pin SD CMD/_ SPI_SCK (SPI)
H4VSSGNDGround Reference Pin (VSS)
H5VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
H6VDDCPowerPower Supply Input (VDDC — 3.3V / 5.0V Standard Logic)
H7GPIO11I/OMultiplexed I/O & Peripheral Pin GPIO11 (General)
H8VDD_AMSPowerPower Supply Input (VDD_AMS — 3.3V / 5.0V Standard Logic)
PIN A1 GPIO6
I/O
Multiplexed I/O & Peripheral Pin GPIO6 (UART, SPI)
Design note: GPIO6/ SPI_RXDFlash_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATWILC1000B-UU-T (MICROCHIP · WLCSP-55)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATWILC1000B-UU-T (WLCSP-55) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATWILC1000B-UU-T (WLCSP-55) - 2. Standard Pinout (Top View)
True package pinout (55 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATWILC1000B-UU-T (WLCSP-55) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATWILC1000B-UU-T (WLCSP-55) - 4. Package Dimensions (D×E×A)
WLCSP-55 · 3.20×3.20mm · Pitch 0.35mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATWILC1000B-UU-T (WLCSP-55) - 5. Recommended Land Pattern
IPC-7351B Footprint (55 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATWILC1000B-UU-T (WLCSP-55) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for ATWILC1000B
P7 · p07_fig01EXACT PACKAGE
ATWILC1000B-UU-T (WLCSP-55) — Figure 3-2. WLCSP Package Pin Assignment
Figure 3-2. WLCSP Package Pin Assignment
P1 · p01_fig01456×280px
ATWILC1000B-UU-T (WLCSP-55) — ATWILC1000B-MUT IEEE® 802.11 b/g/n Link Controller
ATWILC1000B-MUT IEEE® 802.11 b/g/n Link Controller
P6 · p06_fig011415×1284px
ATWILC1000B-UU-T (WLCSP-55) — Figure 3-1. Pin Assignment
Figure 3-1. Pin Assignment
P7 · p07_fig01P7
ATWILC1000B-UU-T (WLCSP-55) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P41 · p41_fig011063×2048px
ATWILC1000B-UU-T (WLCSP-55) — Figure 10-1. ATWILC1000B Reference Schematic
Figure 10-1. ATWILC1000B Reference Schematic
P41 · p41_fig01P41
ATWILC1000B-UU-T (WLCSP-55) — Datasheet Page 41 (p41_fig01)
Datasheet Page 41 (p41_fig01)
P44 · p44_fig011168×816px
ATWILC1000B-UU-T (WLCSP-55) — Figure 11-1. Solder Reflow Profile
Figure 11-1. Solder Reflow Profile
P46 · p46_fig011929×1782px
ATWILC1000B-UU-T (WLCSP-55) — Document Revision History
Document Revision History

Technical Specifications & Part Details (ATWILC1000B-UU-T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATWILC1000B-UU-T (WLCSP-55) is a 55-pin standard electronic & interconnect component featuring a 3.20 × 3.20 × 0.55 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to +85°C with integrated Wi-Fi, UART, SPI, I2C, SDIO, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
26 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.20 × 3.20 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-55)
Pin Count & Lead PitchN / e
55 Pins | Pitch e = 0.35 mm (13.8 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Wi-Fi, UART, SPI, I2C, SDIO, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol55 auto-grouped pins
OK
IPC-7351B Land Pattern55 pads · Pitch 0.35mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-55)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.20 × 3.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.35mm
Pad Size (W × L)Level B
0.17 × 0.17 mm
Pins / Total PadsTopology
55P / 55Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-55
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATWILC1000B-UU-T (WLCSP-55)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATWILC1000B-UU-T (WLCSP-55)?

Manufactured by MICROCHIP, the ATWILC1000B-UU-T is housed in a WLCSP-55 package with 55 pins and a 0.35 mm lead pitch. Key pins include: A1 (GPIO6: Multiplexed I/O & Peripheral Pin GPIO6 (UART, SPI)), A2 (I2C_SCL: Multiplexed I/O & Peripheral Pin I2C_SCL (I2C)), A3 (RESETN: System Enable & Hardware Reset (RESETN)), A4 (XO_N: Multiplexed I/O & Peripheral Pin XO_N (RTC/CLK)), A5 (GND_SXDIG: Ground Reference Pin (GND_SXDIG)), A6 (VDD_SXDIG: Power Supply Input (VDD_SXDIG — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for ATWILC1000B-UU-T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATWILC1000B-UU-T (WLCSP-55) has a nominal body envelope of 3.20 × 3.20 mm, pitch e = 0.35 mm, and 55 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATWILC1000B-UU-T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATWILC1000B-UU-T (MICROCHIP, WLCSP-55) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (55 pins) & ATWILC1000B Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_RXDFLASH_. Supported peripheral buses: UART, SPI.
A2I2C_SCLDigital_IOSignal terminal I2C_SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SCL. Supported peripheral buses: I2C.
A3RESETNDigital_IOActive-low hardware reset terminal (RESETN): pulling this pin Low resets the processor core and peripherals.
A4XO_NDigital_IOSignal terminal XO_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO_N. Supported peripheral buses: RTC/CLK.
A5GND_SXDIGGND0V electrical ground return terminal (GND_SXDIG) for internal core logic, I/O drivers, and analog sub-blocks.
A6VDD_SXDIGPower_InPrimary positive power supply input (VDD_SXDIG) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A7VDDIO_APower_InPrimary positive power supply input (VDDIO_A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B1GPIO16Digital_IOSignal terminal GPIO16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO16. Supported peripheral buses: General.
B2GPIO5Digital_IOSignal terminal GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_TXDFLASH_. Supported peripheral buses: UART, SPI.
B3I2C_SDADigital_IOSignal terminal I2C_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SDA. Supported peripheral buses: I2C.
B4XO_PDigital_IOSignal terminal XO_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO_P. Supported peripheral buses: RTC/CLK.
B5GND_IOGND0V electrical ground return terminal (GND_IO) for internal core logic, I/O drivers, and analog sub-blocks.
B6TP_NNCSignal terminal TP_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TP_N. Supported peripheral buses: General.
B7VDD_RFRX_Power_InPrimary positive power supply input (VDD_RFRX_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B8NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
C1VDDCPower_InPrimary positive power supply input (VDDC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
C2GPIO15Digital_IOSignal terminal GPIO15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO15. Supported peripheral buses: General.
C3GPIO17Digital_IOSignal terminal GPIO17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO17. Supported peripheral buses: General.
C4GPIO18Digital_IOSignal terminal GPIO18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
C5GPIO13Digital_IOSignal terminal GPIO13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO13. Supported peripheral buses: General.
C6TP_PNCSignal terminal TP_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TP_P. Supported peripheral buses: General.
C7GND_RFRX_GND0V electrical ground return terminal (GND_RFRX_) for internal core logic, I/O drivers, and analog sub-blocks.
D1VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D2TEST_MODEDigital_IOSignal terminal TEST_MODE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST_MODE. Supported peripheral buses: General.
D3GPIO4Digital_IOSignal terminal GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_SSNFLASH_. Supported peripheral buses: SPI.
D7VDD_BATTPA_Power_InPrimary positive power supply input (VDD_BATTPA_) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D8GND_BATTPPA_GND0V electrical ground return terminal (GND_BATTPPA_) for internal core logic, I/O drivers, and analog sub-blocks.
E1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E2GPIO1/RTC_CLKDigital_IOSignal terminal GPIO1/RTC_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: RTC/CLK.
E3GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_SCKFLASH_. Supported peripheral buses: SPI.
E7GND_BATTPA_GND0V electrical ground return terminal (GND_BATTPA_) for internal core logic, I/O drivers, and analog sub-blocks.
F1GND_BIASGND0V electrical ground return terminal (GND_BIAS) for internal core logic, I/O drivers, and analog sub-blocks.
F2CHIP_ENDigital_IOSignal terminal CHIP_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General.
F3VREG_BUCKPower_InPrimary positive power supply input (VREG_BUCK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F4SD_DAT3Digital_IOSignal terminal SD_DAT3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_DAT3. Supported peripheral buses: General.
F5GPIO2/IRQNDigital_IOSignal terminal GPIO2/IRQN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
F6GPIO0/ HOST_WAKEDigital_IOSignal terminal GPIO0/ HOST_WAKE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General.
F7GND_AMSGND0V electrical ground return terminal (GND_AMS) for internal core logic, I/O drivers, and analog sub-blocks.
F8TX_PDigital_IOSignal terminal TX_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX_P. Supported peripheral buses: General.
G1GND_BUCKGND0V electrical ground return terminal (GND_BUCK) for internal core logic, I/O drivers, and analog sub-blocks.
G2SD_CLKDigital_IOSignal terminal SD_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_CLK. Supported peripheral buses: General.
G3SD DAT0/_ SPI_TXDDigital_IOSignal terminal SD DAT0/_ SPI_TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_DATATX. Supported peripheral buses: UART, SPI.
G4SD DAT1/_ SPI_SSNDigital_IOSignal terminal SD DAT1/_ SPI_SSN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_SLAVESELECT. Supported peripheral buses: SPI.
G5SD DAT2/_ SPI_RXDDigital_IOSignal terminal SD DAT2/_ SPI_RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_DATARX. Supported peripheral buses: UART, SPI.
G6GPIO12Digital_IOSignal terminal GPIO12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO12. Supported peripheral buses: General.
G7SDIO_SPICFG_Digital_IOSignal terminal SDIO_SPICFG_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDIO_SPICFG_. Supported peripheral buses: SPI.
G8TX_NDigital_IOSignal terminal TX_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX_N. Supported peripheral buses: General.
H1VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
H2VBATT_BUCKPower_InPrimary positive power supply input (VBATT_BUCK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H3SD CMD/_ SPI_SCKDigital_IOSignal terminal SD CMD/_ SPI_SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_CLOCK. Supported peripheral buses: SPI.
H4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
H5VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H6VDDCPower_InPrimary positive power supply input (VDDC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H7GPIO11Digital_IOSignal terminal GPIO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO11. Supported peripheral buses: General.
H8VDD_AMSPower_InPrimary positive power supply input (VDD_AMS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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