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ATTINY1634R-MU (QFN-20-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATTINY1634R-MU

MICROCHIPID: C147878QFN-20-EP(4x4) · 21 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATTINY1634R-MU (QFN-20-EP(4x4))1PA62PA53PA44PA35PA26PA17PA08GND9VCC10PC511PC421EPAD20PA719PB018PB117PB216PB315PC014PC113PC212PC3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.820.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (21/21)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
4PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
5PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
6PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
7PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
8GNDGNDGround Reference Pin (GND)
9VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
10PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
11PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
12PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
13PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
14PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
15PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
16PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
17PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
18PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
19PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
20PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
21EPADGNDExposed Thermal & Ground Pad (EPAD)
PIN 1 PA6
I/O
Multiplexed I/O & Peripheral Pin PA6 (General)
Design note: Signal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATTINY1634R-MU (MICROCHIP · QFN-20-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATTINY1634R-MU (QFN-20-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATTINY1634R-MU (QFN-20-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATTINY1634R-MU (QFN-20-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATTINY1634R-MU (QFN-20-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-20-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATTINY1634R-MU (QFN-20-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATTINY1634R-MU (QFN-20-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for ATTINY1634R
P2 · p02_fig011580×2167px
ATTINY1634R-MU (QFN-20-EP(4x4)) — Figure 1-1. Pinout of ATtiny1634
Figure 1-1. Pinout of ATtiny1634
P2 · p02_fig01P2
ATTINY1634R-MU (QFN-20-EP(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P230 · p230_fig011383×928px
ATTINY1634R-MU (QFN-20-EP(4x4)) — Figure 24-1. Maximum Frequency vs. VCC
Figure 24-1. Maximum Frequency vs. VCC
P281 · p281_fig012025×2369px
ATTINY1634R-MU (QFN-20-EP(4x4)) — 281 ATtiny1634 [DATASHEET]
281 ATtiny1634 [DATASHEET]
P281 · p281_fig01P281
ATTINY1634R-MU (QFN-20-EP(4x4)) — Datasheet Page 281 (p281_fig01)
Datasheet Page 281 (p281_fig01)

Technical Specifications & Part Details (ATTINY1634R-MU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATTINY1634R-MU (QFN-20-EP(4x4)) is a 20-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.80 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
8MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.80 mm (A1=0.03 mm)
Package family: QFN (QFN-20-EP(4x4))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol21 auto-grouped pins
OK
IPC-7351B Land Pattern21 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.60×2.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-20-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.80mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-20-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATTINY1634R-MU (QFN-20-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATTINY1634R-MU (QFN-20-EP(4x4))?

Manufactured by MICROCHIP, the ATTINY1634R-MU is housed in a QFN-20-EP(4x4) package with 21 pins and a 0.50 mm lead pitch. Key pins include: 1 (PA6: Multiplexed I/O & Peripheral Pin PA6 (General)), 2 (PA5: Multiplexed I/O & Peripheral Pin PA5 (General)), 3 (PA4: Multiplexed I/O & Peripheral Pin PA4 (General)), 4 (PA3: Multiplexed I/O & Peripheral Pin PA3 (General)), 5 (PA2: Multiplexed I/O & Peripheral Pin PA2 (General)), 6 (PA1: Multiplexed I/O & Peripheral Pin PA1 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATTINY1634R-MU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATTINY1634R-MU (QFN-20-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 2.60 × 2.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATTINY1634R-MU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATTINY1634R-MU (MICROCHIP, QFN-20-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (21 pins) & ATTINY1634R Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
2PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
4PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
5PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
6PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
7PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
11PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
12PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
13PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
14PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
15PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
16PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
17PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
18PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
19PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
20PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
21EPADGNDBottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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