![CH558L (TQFP-48(7x7)) — 位 名称 访问 描述 复位值 | [7:0] SER1_DLL RW SER1_DLL 是低字节，SER1_DLM 是高字节，两者组成16 位除数，用于由16 位计数器构成的串口波特率产生器。 只有当bLCR_DLAB 为1 时，才能读写这两个寄存器。 该除数 = Fsys * 2 / SER1_DIV / 16 / 波特率 | xxh | [7:0] SER1_DLM RW 80h | UART1 预分频除数寄存器(SER1_DIV)，仅当bLCR_DLAB=1 时有效：](/api/v1/assets/C139617/extracted/figures/p47_fig02.png)
SSOP-20-208mil · 20P
Synchronized Pinout (Symbol / 2D / 3D) (48/48)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | P5 1 . | I/O | Multiplexed I/O & Peripheral Pin P5 1 . (General) |
| 2 | bP4_DRV | I/O | Multiplexed I/O & Peripheral Pin bP4_DRV (General) |
| 3 | bSPI0_PINX_ | I/O | Multiplexed I/O & Peripheral Pin bSPI0_PINX_ (General) |
| 4 | P5 4 . | I/O | Multiplexed I/O & Peripheral Pin P5 4 . (General) |
| 5 | P4.5/A5 | I/O | Multiplexed I/O & Peripheral Pin P4.5/A5 (General) |
| 6 | IO3 | I/O | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | P3.1/TXD | I/O | Multiplexed I/O & Peripheral Pin P3.1/TXD (UART) |
| 8 | P3.2/LED0/INT0 | I/O | Multiplexed I/O & Peripheral Pin P3.2/LED0/INT0 (General) |
| 9 | P3.3/LED1/!A15/INT1 | I/O | Multiplexed I/O & Peripheral Pin P3.3/LED1/!A15/INT1 (General) |
| 10 | P3.4/LEDC/XCS0/T0 | I/O | Multiplexed I/O & Peripheral Pin P3.4/LEDC/XCS0/T0 (General) |
| 11 | P3.5/DA6/T1 | I/O | Multiplexed I/O & Peripheral Pin P3.5/DA6/T1 (General) |
| 12 | P3.6/WR | I/O | Multiplexed I/O & Peripheral Pin P3.6/WR (General) |
| 13 | P3.7/RD | I/O | Multiplexed I/O & Peripheral Pin P3.7/RD (General) |
| 14 | P4.3/A3 | I/O | Multiplexed I/O & Peripheral Pin P4.3/A3 (General) |
| 15 | P4.2/PWM3_/CAP3_/A2 | I/O | Multiplexed I/O & Peripheral Pin P4.2/PWM3_/CAP3_/A2 (PWM) |
| 16 | P4.6/XI/SCS_ | I/O | Multiplexed I/O & Peripheral Pin P4.6/XI/SCS_ (RTC/CLK) |
| 17 | P4.7/XO/SCK_ | I/O | Multiplexed I/O & Peripheral Pin P4.7/XO/SCK_ (SPI, RTC/CLK) |
| 18 | GND/VSS | GND | Ground Reference Pin (GND/VSS) |
| 19 | P4.1/A1 | I/O | Multiplexed I/O & Peripheral Pin P4.1/A1 (General) |
| 20 | P4.0/LED2/A0/RXD1 | I/O | Multiplexed I/O & Peripheral Pin P4.0/LED2/A0/RXD1 (UART) |
| 21 | P2.0/A8 | I/O | Multiplexed I/O & Peripheral Pin P2.0/A8 (General) |
| 22 | P2.1/A9 | I/O | Multiplexed I/O & Peripheral Pin P2.1/A9 (General) |
| 23 | P2.2/A10 | I/O | Multiplexed I/O & Peripheral Pin P2.2/A10 (General) |
| 24 | P2.3/A11 | I/O | Multiplexed I/O & Peripheral Pin P2.3/A11 (General) |
| 25 | P2.4/A12 | I/O | Multiplexed I/O & Peripheral Pin P2.4/A12 (General) |
| 26 | IO21 | I/O | GPIO21 / RTC_GPIO21 |
| 27 | P2.6/RXD1/A14 | I/O | Multiplexed I/O & Peripheral Pin P2.6/RXD1/A14 (UART) |
| 28 | P2.7/TXD1/DA7/A15 | I/O | Multiplexed I/O & Peripheral Pin P2.7/TXD1/DA7/A15 (UART) |
| 29 | P5.5/!A15/XA | I/O | Multiplexed I/O & Peripheral Pin P5.5/!A15/XA (General) |
| 30 | P5.4/ALE/XB | I/O | Multiplexed I/O & Peripheral Pin P5.4/ALE/XB (General) |
| 31 | P5.1/DP | I/O | Multiplexed I/O & Peripheral Pin P5.1/DP (General) |
| 32 | P5.0/DM | I/O | Multiplexed I/O & Peripheral Pin P5.0/DM (General) |
| 33 | P0.7/AD7/UDCD | I/O | Multiplexed I/O & Peripheral Pin P0.7/AD7/UDCD (General) |
| 34 | P0.6/AD6/URI | I/O | Multiplexed I/O & Peripheral Pin P0.6/AD6/URI (General) |
| 35 | P0.5/AD5/UDSR | I/O | Multiplexed I/O & Peripheral Pin P0.5/AD5/UDSR (General) |
| 36 | P0.4/AD4/UCTS | I/O | Multiplexed I/O & Peripheral Pin P0.4/AD4/UCTS (General) |
| 37 | P0.3/AD3/TXD | I/O | Multiplexed I/O & Peripheral Pin P0.3/AD3/TXD (UART) |
| 38 | P0.2/AD2/RXD | I/O | Multiplexed I/O & Peripheral Pin P0.2/AD2/RXD (UART) |
| 39 | P0.1/AD1/URTS | I/O | Multiplexed I/O & Peripheral Pin P0.1/AD1/URTS (General) |
| 40 | P0.0/AD0/UDTR | I/O | Multiplexed I/O & Peripheral Pin P0.0/AD0/UDTR (General) |
| 41 | VIN5 | Power | Power Supply Input (VIN5 — 3.3V / 5.0V Standard Logic) |
| 42 | VDD33 | Power | Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic) |
| 43 | P1.0/AIN0/T2/CAP1 | I/O | Multiplexed I/O & Peripheral Pin P1.0/AIN0/T2/CAP1 (ADC) |
| 44 | P1.1/AIN1/T2EX/CAP2 | I/O | Multiplexed I/O & Peripheral Pin P1.1/AIN1/T2EX/CAP2 (ADC) |
| 45 | P1.2/AIN2/PWM3/CAP3 | I/O | Multiplexed I/O & Peripheral Pin P1.2/AIN2/PWM3/CAP3 (ADC, PWM) |
| 46 | P1.3/AIN3 | I/O | Multiplexed I/O & Peripheral Pin P1.3/AIN3 (ADC) |
| 47 | P1.4/AIN4/SCS | I/O | Multiplexed I/O & Peripheral Pin P1.4/AIN4/SCS (ADC) |
| 48 | P1.5/AIN5/MOSI | I/O | Multiplexed I/O & Peripheral Pin P1.5/AIN5/MOSI (SPI, ADC) |
PIN 1 P5 1 .
I/OMultiplexed I/O & Peripheral Pin P5 1 . (General)
Design note: Signal terminal P5 1 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5 1 .. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
TQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH558
P1 · p01_fig011745×916px
P2 · p02_fig011752×1371px
P2 · p02_fig01P2
P46 · p46_fig011757×2656px
P47 · p47_fig011757×1008px
P47 · p47_fig021757×734px
Technical Specifications & Part Details (CH558L)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH558L (TQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
12MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol48 auto-grouped pins
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH558 (2)
TQFP-48(7x7) · 48P
Mechanical Dimensions & Land Pattern (TQFP-48(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TQFP-48(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH558L (TQFP-48(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH558L (TQFP-48(7x7))?
Manufactured by WCH, the CH558L is housed in a TQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (P5 1 .: Multiplexed I/O & Peripheral Pin P5 1 . (General)), 2 (bP4_DRV: Multiplexed I/O & Peripheral Pin bP4_DRV (General)), 3 (bSPI0_PINX_: Multiplexed I/O & Peripheral Pin bSPI0_PINX_ (General)), 4 (P5 4 .: Multiplexed I/O & Peripheral Pin P5 4 . (General)), 5 (P4.5/A5: Multiplexed I/O & Peripheral Pin P4.5/A5 (General)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).
What are the IPC-7351B PCB Footprint dimensions for CH558L?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH558L (TQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH558L?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH558L (WCH, TQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (48 pins) & CH558 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | P5 1 . | Digital_IO | Signal terminal P5 1 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5 1 .. Supported peripheral buses: General. |
| 2 | bP4_DRV | Digital_IO | Signal terminal bP4_DRV (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: bP4_DRV. Supported peripheral buses: General. |
| 3 | bSPI0_PINX_ | Digital_IO | Signal terminal bSPI0_PINX_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: bSPI0_PINX_. Supported peripheral buses: General. |
| 4 | P5 4 . | Digital_IO | Signal terminal P5 4 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5 4 .. Supported peripheral buses: General. |
| 5 | P4.5/A5 | Digital_IO | Signal terminal P4.5/A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.5/A5. Supported peripheral buses: General. |
| 6 | IO3 | Digital_IO | GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap) |
| 7 | P3.1/TXD | Digital_IO | Signal terminal P3.1/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/TXD. Supported peripheral buses: UART. |
| 8 | P3.2/LED0/INT0 | Digital_IO | Signal terminal P3.2/LED0/INT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.2/LED0/INT0. Supported peripheral buses: General. |
| 9 | P3.3/LED1/!A15/INT1 | Digital_IO | Signal terminal P3.3/LED1/!A15/INT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3/LED1/!A15/INT1. Supported peripheral buses: General. |
| 10 | P3.4/LEDC/XCS0/T0 | Digital_IO | Signal terminal P3.4/LEDC/XCS0/T0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/LEDC/XCS0/T0. Supported peripheral buses: General. |
| 11 | P3.5/DA6/T1 | Digital_IO | Signal terminal P3.5/DA6/T1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.5/DA6/T1. Supported peripheral buses: General. |
| 12 | P3.6/WR | Digital_IO | Signal terminal P3.6/WR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.6/WR. Supported peripheral buses: General. |
| 13 | P3.7/RD | Digital_IO | Signal terminal P3.7/RD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.7/RD. Supported peripheral buses: General. |
| 14 | P4.3/A3 | Digital_IO | Signal terminal P4.3/A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.3/A3. Supported peripheral buses: General. |
| 15 | P4.2/PWM3_/CAP3_/A2 | Digital_IO | Signal terminal P4.2/PWM3_/CAP3_/A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.2/PWM3_/CAP3_/A2. Supported peripheral buses: PWM. |
| 16 | P4.6/XI/SCS_ | Digital_IO | Signal terminal P4.6/XI/SCS_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.6/XI/SCS_. Supported peripheral buses: RTC/CLK. |
| 17 | P4.7/XO/SCK_ | Digital_IO | Signal terminal P4.7/XO/SCK_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, RTC/CLK. |
| 18 | GND/VSS | GND | 0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 19 | P4.1/A1 | Digital_IO | Signal terminal P4.1/A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.1/A1. Supported peripheral buses: General. |
| 20 | P4.0/LED2/A0/RXD1 | Digital_IO | Signal terminal P4.0/LED2/A0/RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.0/LED2/A0/RXD1. Supported peripheral buses: UART. |
| 21 | P2.0/A8 | Digital_IO | Signal terminal P2.0/A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.0/A8. Supported peripheral buses: General. |
| 22 | P2.1/A9 | Digital_IO | Signal terminal P2.1/A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.1/A9. Supported peripheral buses: General. |
| 23 | P2.2/A10 | Digital_IO | Signal terminal P2.2/A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.2/A10. Supported peripheral buses: General. |
| 24 | P2.3/A11 | Digital_IO | Signal terminal P2.3/A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.3/A11. Supported peripheral buses: General. |
| 25 | P2.4/A12 | Digital_IO | Signal terminal P2.4/A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.4/A12. Supported peripheral buses: General. |
| 26 | IO21 | Digital_IO | GPIO21 / RTC_GPIO21 |
| 27 | P2.6/RXD1/A14 | Digital_IO | Signal terminal P2.6/RXD1/A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.6/RXD1/A14. Supported peripheral buses: UART. |
| 28 | P2.7/TXD1/DA7/A15 | Digital_IO | Signal terminal P2.7/TXD1/DA7/A15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.7/TXD1/DA7/A15. Supported peripheral buses: UART. |
| 29 | P5.5/!A15/XA | Digital_IO | Signal terminal P5.5/!A15/XA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.5/!A15/XA. Supported peripheral buses: General. |
| 30 | P5.4/ALE/XB | Digital_IO | Signal terminal P5.4/ALE/XB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.4/ALE/XB. Supported peripheral buses: General. |
| 31 | P5.1/DP | Digital_IO | Signal terminal P5.1/DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.1/DP. Supported peripheral buses: General. |
| 32 | P5.0/DM | Digital_IO | Signal terminal P5.0/DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.0/DM. Supported peripheral buses: General. |
| 33 | P0.7/AD7/UDCD | Digital_IO | Signal terminal P0.7/AD7/UDCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.7/AD7/UDCD. Supported peripheral buses: General. |
| 34 | P0.6/AD6/URI | Digital_IO | Signal terminal P0.6/AD6/URI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.6/AD6/URI. Supported peripheral buses: General. |
| 35 | P0.5/AD5/UDSR | Digital_IO | Signal terminal P0.5/AD5/UDSR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.5/AD5/UDSR. Supported peripheral buses: General. |
| 36 | P0.4/AD4/UCTS | Digital_IO | Signal terminal P0.4/AD4/UCTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.4/AD4/UCTS. Supported peripheral buses: General. |
| 37 | P0.3/AD3/TXD | Digital_IO | Signal terminal P0.3/AD3/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.3/AD3/TXD. Supported peripheral buses: UART. |
| 38 | P0.2/AD2/RXD | Digital_IO | Signal terminal P0.2/AD2/RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.2/AD2/RXD. Supported peripheral buses: UART. |
| 39 | P0.1/AD1/URTS | Digital_IO | Signal terminal P0.1/AD1/URTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.1/AD1/URTS. Supported peripheral buses: General. |
| 40 | P0.0/AD0/UDTR | Digital_IO | Signal terminal P0.0/AD0/UDTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P0.0/AD0/UDTR. Supported peripheral buses: General. |
| 41 | VIN5 | Power_In | Primary positive power supply input (VIN5) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 42 | VDD33 | Power_In | Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 43 | P1.0/AIN0/T2/CAP1 | Analog | Signal terminal P1.0/AIN0/T2/CAP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.0/AIN0/T2/CAP1. Supported peripheral buses: ADC. |
| 44 | P1.1/AIN1/T2EX/CAP2 | Analog | Signal terminal P1.1/AIN1/T2EX/CAP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.1/AIN1/T2EX/CAP2. Supported peripheral buses: ADC. |
| 45 | P1.2/AIN2/PWM3/CAP3 | Analog | Signal terminal P1.2/AIN2/PWM3/CAP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.2/AIN2/PWM3/CAP3. Supported peripheral buses: ADC, PWM. |
| 46 | P1.3/AIN3 | Analog | Signal terminal P1.3/AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.3/AIN3. Supported peripheral buses: ADC. |
| 47 | P1.4/AIN4/SCS | Analog | Signal terminal P1.4/AIN4/SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.4/AIN4/SCS. Supported peripheral buses: ADC. |
| 48 | P1.5/AIN5/MOSI | Digital_IO | Signal terminal P1.5/AIN5/MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, ADC. |