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STM32L412R8I6 (UFBGA-64) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L412R8I6

STUFBGA-64 · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L412R8I6 (UFBGA-64)A1PC14OSC32 INA2PC13A3PB9A4PB4(NJTRST)A5PB3 (JTDO/TRA6PA15(JTDI)A7PA14 (JTCK/SA8PA13 (JTMS/SB1IOB1B2VBATB3PB8B4PH3BOOT0 - (B5PD2B6PC11B7PC10B8PA12C1PH0OSC IN -_C2VSSC3PB7C4PB5C5PC12C6PA10C7PA9C8PA11D1PH1OSC OUT -D2VDDD3PB6D4VSSD5VSSD6VSSD7PA8D8PC9H8PB12H7PB11H6PC5H5PC4H4PA7H3PA4H2PA1H1VDDA/VREF+G8PB13G7PB10G6PB2G5PB1G4PA6G3PA3G2PA0G1PC3F8PB14F7PB15F6PC6F5PB0F4PA5F3PA2F2PC2F1VSSA/VREF -E8PC8E7PC7E6VDDE5VDDUSBE4VDDE3PC0E2PC1E1NRSTGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1A2B2C2D2E2F2G2H2A3B3C3D3E3F3G3H3A4B4C4D4E4F4G4H4A5B5C5D5E5F5G5H5A6B6C6D6E6F6G6H6A7B7C7D7E7F7G7H7A8B8C8D8E8F8G8H8E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC14OSC32 IN -_ (PC14)I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (PC14) (RTC/CLK)
A2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
A3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI)
A4PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (SPI, I2C, SWD/JTAG)
A5PB3 (JTDO/TRACESW O)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO/TRACESW O) (UART, PWM, SWD/JTAG)
A6PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
A7PA14 (JTCK/SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK/SWCLK) (SWD/JTAG)
A8PA13 (JTMS/SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS/SWDIO) (USB, SWD/JTAG)
B1IOB1I/OGeneral Purpose Digital I/O Pin IOB1
B2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B4PH3BOOT0 - (BOOT0)I/OMultiplexed I/O & Peripheral Pin PH3BOOT0 - (BOOT0) (General)
B5PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
B6PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
B7PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
B8PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART)
C1PH0OSC IN -_ (PH0)I/OMultiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
C2VSSGNDGround Reference Pin (VSS)
C3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
C4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, I2C)
C5PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
C6PA10I/OMultiplexed I/O & Peripheral Pin PA10 (USB, UART, PWM)
C7PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
C8PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, PWM)
D1PH1OSC OUT -_ (PH1)I/OMultiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)
D2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D3PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
D4VSSGNDGround Reference Pin (VSS)
D5VSSGNDGround Reference Pin (VSS)
D6VSSGNDGround Reference Pin (VSS)
D7PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D8PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (I2C, ADC)
E3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (I2C, ADC)
E4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E5VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
E6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E7PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E8PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F1VSSA/VREF -GNDGround Reference Pin (VSSA/VREF -)
F2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
F3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (ADC, PWM)
F4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
F5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (SPI, ADC)
F6PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F7PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
F8PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
G1PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
G2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (PWM, RTC/CLK)
G3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
G4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
G5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC)
G6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, PWM)
G8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
H1VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V))
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, PWM)
H3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI)
H4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
H5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
H6PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
H7PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, PWM)
H8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
PIN A1 PC14OSC32 IN -_ (PC14)
I/O
Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (PC14) (RTC/CLK)
Design note: Alt: EVENTOUT | Add: OSC32_IN
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 42 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L412R8I6 (ST · UFBGA-64)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L412R8I6 (UFBGA-64) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L412R8I6 (UFBGA-64) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L412R8I6 (UFBGA-64) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L412R8I6 (UFBGA-64) - 4. Package Dimensions (D×E×A)
UFBGA-64 · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L412R8I6 (UFBGA-64) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L412R8I6 (UFBGA-64) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (42 figures · Page 1/4)
Showing 1–12 of 42 uncropped original figures for STM32L412 / STM32G473
P50 · p50_fig01EXACT PACKAGE
STM32L412R8I6 (UFBGA-64) — Figure 5. STM32L412Rx LQFP64 pinout(1)
Figure 5. STM32L412Rx LQFP64 pinout(1)
P50 · p50_fig02EXACT PACKAGE
STM32L412R8I6 (UFBGA-64) — PA0
PA0
P51 · p51_fig01EXACT PACKAGE
STM32L412R8I6 (UFBGA-64) — Figure 7. STM32L412Rx UFBGA64 ballout(1) 1 2 3 4 5 6 7 8 PC14- OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13 B C D
Figure 7. STM32L412Rx UFBGA64 ballout(1) 1 2 3 4 5 6 7 8 PC14- OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13 B C D
P51 · p51_fig02EXACT PACKAGE
STM32L412R8I6 (UFBGA-64) — F
F
P169 · p169_fig01EXACT PACKAGE
STM32L412R8I6 (UFBGA-64) — Figure 42. UFBGA64 - Outline
Figure 42. UFBGA64 - Outline
P170 · p170_fig01EXACT PACKAGE
STM32L412R8I6 (UFBGA-64) — Figure 43. UFBGA64 - Recommended footprint
Figure 43. UFBGA64 - Recommended footprint
P1 · p01_fig01881×489px
STM32L412R8I6 (UFBGA-64) — • RTC with HW calendar, alarms and calibration
• RTC with HW calendar, alarms and calibration
P74 · p74_fig011546×1275px
STM32L412R8I6 (UFBGA-64) — Figure 18. Power supply scheme
Figure 18. Power supply scheme
P117 · p117_fig011546×702px
STM32L412R8I6 (UFBGA-64) — Figure 23. Typical application with an 8 MHz crystal
Figure 23. Typical application with an 8 MHz crystal
P118 · p118_fig011546×702px
STM32L412R8I6 (UFBGA-64) — Figure 24. Typical application with a 32.768 kHz crystal
Figure 24. Typical application with a 32.768 kHz crystal
P167 · p167_fig011546×1155px
STM32L412R8I6 (UFBGA-64) — Figure 39. LQFP64 - Recommended footprint
Figure 39. LQFP64 - Recommended footprint
P174 · p174_fig011546×1133px
STM32L412R8I6 (UFBGA-64) — Figure 47. LQFP48 - Recommended footprint
Figure 47. LQFP48 - Recommended footprint
Page 1 / 4 (42 extracted figures)

Technical Specifications & Part Details (STM32L412R8I6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L412R8I6 (UFBGA-64) is a 64-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.53 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
49 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-64)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3BOOT0 - (BOOT0)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32L412 / STM32G473 (20)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (UFBGA-64)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-64
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L412R8I6 (UFBGA-64)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L412R8I6 (UFBGA-64)?

Manufactured by ST, the STM32L412R8I6 is housed in a UFBGA-64 package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PC14OSC32 IN -_ (PC14): Multiplexed I/O & Peripheral Pin PC14OSC32 IN -_ (PC14) (RTC/CLK)), A2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), A3 (PB9: Multiplexed I/O & Peripheral Pin PB9 (SPI)), A4 (PB4(NJTRST): Multiplexed I/O & Peripheral Pin PB4(NJTRST) (SPI, I2C, SWD/JTAG)), A5 (PB3 (JTDO/TRACESW O): Multiplexed I/O & Peripheral Pin PB3 (JTDO/TRACESW O) (UART, PWM, SWD/JTAG)), A6 (PA15(JTDI): Multiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32L412R8I6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L412R8I6 (UFBGA-64) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L412R8I6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L412R8I6 (ST, UFBGA-64) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32L412 / STM32G473 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC14OSC32 IN -_ (PC14)Digital_IOSignal terminal PC14OSC32 IN -_ (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14OSC32 IN -_ (PC14). Supported peripheral buses: RTC/CLK.
A2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
A3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSEVENTOUT. Supported peripheral buses: SPI.
A4PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOUSART1CTS. Supported peripheral buses: SPI, I2C, SWD/JTAG.
A5PB3 (JTDO/TRACESW O)Digital_IOSignal terminal PB3 (JTDO/TRACESW O) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB3 (JTDO/TRACESW O). Supported peripheral buses: UART, PWM, SWD/JTAG.
A6PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
A7PA14 (JTCK/SWCLK)Digital_IOSignal terminal PA14 (JTCK/SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK/SWCLK). Supported peripheral buses: SWD/JTAG.
A8PA13 (JTMS/SWDIO)Digital_IOSignal terminal PA13 (JTMS/SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/SWDIO). Supported peripheral buses: USB, SWD/JTAG.
B1IOB1Digital_IOGeneral Purpose Digital I/O Pin IOB1
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C.
B4PH3BOOT0 - (BOOT0)Digital_IOSignal terminal PH3BOOT0 - (BOOT0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3BOOT0 - (BOOT0). Supported peripheral buses: General.
B5PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
B6PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
B7PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
B8PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART.
C1PH0OSC IN -_ (PH0)Digital_IOSignal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK.
C2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C.
C4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: UART, I2C.
C5PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
C6PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: USB, UART, PWM.
C7PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
C8PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOCOMP1OUT. Supported peripheral buses: UART, SPI, PWM.
D1PH1OSC OUT -_ (PH1)Digital_IOSignal terminal PH1OSC OUT -_ (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT -_ (PH1). Supported peripheral buses: RTC/CLK.
D2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D3PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C.
D4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D7PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D8PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: I2C, ADC.
E3PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: I2C, ADC.
E4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E5VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E7PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E8PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F1VSSA/VREF -GND0V electrical ground return terminal (VSSA/VREF -) for internal core logic, I/O drivers, and analog sub-blocks.
F2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
F3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: ADC, PWM.
F4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCKLPTIM2ETR. Supported peripheral buses: SPI, ADC, PWM.
F5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSUSART3CK. Supported peripheral buses: SPI, ADC.
F6PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F7PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_TSCG1IO4. Supported peripheral buses: SPI, RTC/CLK.
F8PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
G1PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
G2PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: PWM, RTC/CLK.
G3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: ADC, PWM.
G4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: UART, ADC.
G5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC.
G6PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
G7PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKUSART3TX. Supported peripheral buses: SPI, PWM.
G8PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKUSART3CTS. Supported peripheral buses: UART, SPI, PWM.
H1VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, PWM.
H3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSUSART2CK. Supported peripheral buses: SPI.
H4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
H5PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC.
H6PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC.
H7PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: UART, PWM.
H8PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSSUSART3CK. Supported peripheral buses: UART, SPI.
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