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SN74HC595DR (SOIC-16) — Symbol, Footprint IPC-7351B & 3D STEP Model

SN74HC595DR

TIID: C10092SOIC-16 · 16 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SN74HC595DR (SOIC-16)1Q B2Q C3Q D4Q E5Q F6Q G7Q H8GND16VCC15Q A14SER13OE12RCLK11SRCLK10SRCLR9Q H'Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.815.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=3.90mm · Pitch e=1.27mmD=9.90mm-6-5-4-3-2-1012345676543210-1-2-3-4-5-6-7mm
3. 3D CAD MODEL
Package Body: 3.90mm × 9.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1Q BI/OMultiplexed I/O & Peripheral Pin Q B (General)
2Q CI/OMultiplexed I/O & Peripheral Pin Q C (General)
3Q DI/OMultiplexed I/O & Peripheral Pin Q D (General)
4Q EI/OMultiplexed I/O & Peripheral Pin Q E (General)
5Q FI/OMultiplexed I/O & Peripheral Pin Q F (General)
6Q GI/OMultiplexed I/O & Peripheral Pin Q G (General)
7Q HI/OMultiplexed I/O & Peripheral Pin Q H (General)
8GNDGNDGround Reference Pin (GND)
9Q H'I/OMultiplexed I/O & Peripheral Pin Q H' (General)
10SRCLRI/OMultiplexed I/O & Peripheral Pin SRCLR (General)
11SRCLKI/OMultiplexed I/O & Peripheral Pin SRCLK (General)
12RCLKI/OMultiplexed I/O & Peripheral Pin RCLK (General)
13OEI/OMultiplexed I/O & Peripheral Pin OE (General)
14SERI/OMultiplexed I/O & Peripheral Pin SER (General)
15Q AI/OMultiplexed I/O & Peripheral Pin Q A (General)
16VCCPowerPower Supply Input (VCC — 2 V to 6 V)
PIN 1 Q B
I/O
Multiplexed I/O & Peripheral Pin Q B (General)
Design note: Q Output B
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SN74HC595DR (TI · SOIC-16)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SN74HC595DR (SOIC-16) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SN74HC595DR (SOIC-16) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SN74HC595DR (SOIC-16) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SN74HC595DR (SOIC-16) - 4. Package Dimensions (D×E×A)
SOIC-16 · 3.90×9.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
SN74HC595DR (SOIC-16) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
SN74HC595DR (SOIC-16) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for SN74HC595DR
P4 · p04_fig01EXACT PACKAGE
SN74HC595DR (SOIC-16) — 6 Pin Configuration and Functions
6 Pin Configuration and Functions
P4 · p04_fig02EXACT PACKAGE
SN74HC595DR (SOIC-16) — Pin Functions
Pin Functions
P1 · p01_fig01837×1141px
SN74HC595DR (SOIC-16) — the end of the data sheet. • LED Displays • Servers
the end of the data sheet. • LED Displays • Servers
P4 · p04_fig02P4
SN74HC595DR (SOIC-16) — Datasheet Page 4 (p04_fig02)
Datasheet Page 4 (p04_fig02)
P14 · p14_fig011197×1014px
SN74HC595DR (SOIC-16) — Figure 5. Typical Application Schematic
Figure 5. Typical Application Schematic
P14 · p14_fig01P14
SN74HC595DR (SOIC-16) — Datasheet Page 14 (p14_fig01)
Datasheet Page 14 (p14_fig01)
P15 · p15_fig01850×810px
SN74HC595DR (SOIC-16) — Figure 6. SN75HC595 tpd vs. VCC
Figure 6. SN75HC595 tpd vs. VCC
P16 · p16_fig011609×364px
SN74HC595DR (SOIC-16) — Figure 7. Layout Diagram
Figure 7. Layout Diagram
P24 · p24_fig011850×1977px
SN74HC595DR (SOIC-16) — MECHANICAL DATA - FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER - eee
MECHANICAL DATA - FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER - eee
P25 · p25_fig011711×2217px
SN74HC595DR (SOIC-16) — MECHANICAL DATA - ) (R-PDSO-G16) PLASTIC SMALL OUTLINE - « »
MECHANICAL DATA - ) (R-PDSO-G16) PLASTIC SMALL OUTLINE - « »
P25 · p25_fig01P25
SN74HC595DR (SOIC-16) — Datasheet Page 25 (p25_fig01)
Datasheet Page 25 (p25_fig01)
P26 · p26_fig011704×1706px
SN74HC595DR (SOIC-16) — LAND PATTERN DATA - D _(R-PDSO-Gi16) PLASTIC SMALL OUTLINE - =| =-16x0,55
LAND PATTERN DATA - D _(R-PDSO-Gi16) PLASTIC SMALL OUTLINE - =| =-16x0,55
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (SN74HC595DR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SN74HC595DR (SOIC-16) is a 16-pin standard electronic & interconnect component featuring a 9.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2 V to 6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
2 V to 6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.90 × 3.90 × 1.75 mm (A1=0.00 mm)
Package family: SOIC (SOIC-16)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-16)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-16
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SN74HC595DR (SOIC-16)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SN74HC595DR (SOIC-16)?

Manufactured by TI, the SN74HC595DR is housed in a SOIC-16 package with 16 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2 V to 6 V. Key pins include: 1 (Q B: Multiplexed I/O & Peripheral Pin Q B (General)), 2 (Q C: Multiplexed I/O & Peripheral Pin Q C (General)), 3 (Q D: Multiplexed I/O & Peripheral Pin Q D (General)), 4 (Q E: Multiplexed I/O & Peripheral Pin Q E (General)), 5 (Q F: Multiplexed I/O & Peripheral Pin Q F (General)), 6 (Q G: Multiplexed I/O & Peripheral Pin Q G (General)).

What are the IPC-7351B PCB Footprint dimensions for SN74HC595DR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SN74HC595DR (SOIC-16) has a nominal body envelope of 3.90 × 9.90 mm, pitch e = 1.27 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SN74HC595DR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SN74HC595DR (TI, SOIC-16) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & SN74HC595DR Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1Q BDigital_IOSignal terminal Q B (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q B. Supported peripheral buses: General.
2Q CDigital_IOSignal terminal Q C (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q C. Supported peripheral buses: General.
3Q DDigital_IOSignal terminal Q D (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q D. Supported peripheral buses: General.
4Q EDigital_IOSignal terminal Q E (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q E. Supported peripheral buses: General.
5Q FDigital_IOSignal terminal Q F (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q F. Supported peripheral buses: General.
6Q GDigital_IOSignal terminal Q G (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q G. Supported peripheral buses: General.
7Q HDigital_IOSignal terminal Q H (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q H. Supported peripheral buses: General.
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9Q H'Digital_IOSignal terminal Q H' (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q H'. Supported peripheral buses: General.
10SRCLRDigital_IOSignal terminal SRCLR (I/O, 2 V to 6 V domain). Multiplexed alternate functions: SRCLR. Supported peripheral buses: General.
11SRCLKDigital_IOSignal terminal SRCLK (I/O, 2 V to 6 V domain). Multiplexed alternate functions: SRCLK. Supported peripheral buses: General.
12RCLKDigital_IOSignal terminal RCLK (I/O, 2 V to 6 V domain). Multiplexed alternate functions: RCLK. Supported peripheral buses: General.
13OEDigital_IOSignal terminal OE (I/O, 2 V to 6 V domain). Multiplexed alternate functions: OE. Supported peripheral buses: General.
14SERDigital_IOSignal terminal SER (I/O, 2 V to 6 V domain). Multiplexed alternate functions: SER. Supported peripheral buses: General.
15Q ADigital_IOSignal terminal Q A (I/O, 2 V to 6 V domain). Multiplexed alternate functions: Q A. Supported peripheral buses: General.
16VCCPower_InPrimary positive power supply input (VCC) operating in the 2 V to 6 V domain (Max rating: 6.0V).
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