TC7650CPD (PDIP-14) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of TC7650CPD (PDIP-14)?

Manufactured by MICROCHIP, the TC7650CPD is housed in a PDIP-14 package with 14 pins and a 2.54 mm lead pitch. Key pins include: 1 (CB: Multiplexed I/O & Peripheral Pin CB (General)), 2 (CA: Multiplexed I/O & Peripheral Pin CA (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (INPUT -: Multiplexed I/O & Peripheral Pin INPUT - (General)), 5 (+INPUT: Multiplexed I/O & Peripheral Pin +INPUT (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for TC7650CPD?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TC7650CPD (PDIP-14) has a nominal body envelope of 6.80 × 17.24 mm, pitch e = 2.54 mm, and 14 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TC7650CPD?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TC7650CPD (MICROCHIP, PDIP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.80mm × 17.24mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (14/14)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	CB	I/O	Multiplexed I/O & Peripheral Pin CB (General)
2	CA	I/O	Multiplexed I/O & Peripheral Pin CA (General)
3	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
4	INPUT -	I/O	Multiplexed I/O & Peripheral Pin INPUT - (General)
5	+INPUT	I/O	Multiplexed I/O & Peripheral Pin +INPUT (General)
6	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
7	VSS	GND	Ground Reference Pin (VSS)
8	C RETN	I/O	Multiplexed I/O & Peripheral Pin C RETN (General)
9	OUTPUT CLAMP	I/O	Multiplexed I/O & Peripheral Pin OUTPUT CLAMP (General)
10	OUTPUT	I/O	Multiplexed I/O & Peripheral Pin OUTPUT (General)
11	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
12	INTCLKOUT	I/O	Multiplexed I/O & Peripheral Pin INTCLKOUT (General)
13	EXTCLKIN	I/O	Multiplexed I/O & Peripheral Pin EXTCLKIN (General)
14	INT/EXT	I/O	Multiplexed I/O & Peripheral Pin INT/EXT (General)

PIN 1 CB

I/O

Multiplexed I/O & Peripheral Pin CB (General)

Design note: Signal terminal CB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CB. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

TC7650CPD (PDIP-14) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

TC7650CPD (PDIP-14) - 2. Standard Pinout (Top View)

True package pinout (14 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

TC7650CPD (PDIP-14) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

TC7650CPD (PDIP-14) - 4. Package Dimensions (D×E×A)

PDIP-14 · 6.80×17.24mm · Pitch 2.54mmExpand ›

5. Recommended Land PatternLAND PATTERN

TC7650CPD (PDIP-14) - 5. Recommended Land Pattern

IPC-7351B Footprint (14 Pads)Expand ›

6. Application SchematicSCHEMATIC

TC7650CPD (PDIP-14) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)

Showing 1–6 of 6 uncropped original figures for TC7650

P1 · p01_fig021783×1576px

TC7650

P1 · p01_fig02P1

Datasheet Page 1 (p01_fig02)

P7 · p07_fig01867×1673px

FIGURE 3-6: INPUT GUARD CONNECTION

P9 · p09_fig011777×2290px

Package marking information not available at this time.

P1 · p01_fig01All Packages in PDF

P2 · p02_fig01All Packages in PDF

Functional Block Diagram

Technical Specifications & Part Details (TC7650CPD)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:TC7650CPD (PDIP-14) is a 14-pin standard electronic & interconnect component featuring a 17.24 × 6.80 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 0°C to +70°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

0°C to +70°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

2MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

17.24 × 6.80 × 4.20 mm (A1=0.51 mm)

Package family: DIP (PDIP-14)

Pin Count & Lead PitchN / e

14 Pins | Pitch e = 2.54 mm (100.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol14 auto-grouped pins

IPC-7351B Land Pattern14 pads · Pitch 2.54mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-14)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

17.24 × 6.80 mm

Height (A) & Pitch (e)IPC-7351B

A=4.20mm · e=2.54mm

Pad Size (W × L)Level B

1.60 × 1.60 mm

Pins / Total PadsTopology

14P / 14Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PDIP-14	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — TC7650CPD (PDIP-14)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of TC7650CPD (PDIP-14)?

Manufactured by MICROCHIP, the TC7650CPD is housed in a PDIP-14 package with 14 pins and a 2.54 mm lead pitch. Key pins include: 1 (CB: Multiplexed I/O & Peripheral Pin CB (General)), 2 (CA: Multiplexed I/O & Peripheral Pin CA (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (INPUT -: Multiplexed I/O & Peripheral Pin INPUT - (General)), 5 (+INPUT: Multiplexed I/O & Peripheral Pin +INPUT (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for TC7650CPD?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TC7650CPD (PDIP-14) has a nominal body envelope of 6.80 × 17.24 mm, pitch e = 2.54 mm, and 14 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TC7650CPD?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TC7650CPD (MICROCHIP, PDIP-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (14 pins) & TC7650 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	CB	Digital_IO	Signal terminal CB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CB. Supported peripheral buses: General.
2	CA	Digital_IO	Signal terminal CA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CA. Supported peripheral buses: General.
3	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4	INPUT -	Digital_IO	Signal terminal INPUT - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INPUT -. Supported peripheral buses: General.
5	+INPUT	Digital_IO	Signal terminal +INPUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: +INPUT. Supported peripheral buses: General.
6	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
8	C RETN	Digital_IO	Signal terminal C RETN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: C RETN. Supported peripheral buses: General.
9	OUTPUT CLAMP	Digital_IO	Signal terminal OUTPUT CLAMP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUTPUT CLAMP. Supported peripheral buses: General.
10	OUTPUT	Digital_IO	Signal terminal OUTPUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUTPUT. Supported peripheral buses: General.
11	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12	INTCLKOUT	Digital_IO	Signal terminal INTCLKOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INTCLKOUT. Supported peripheral buses: General.
13	EXTCLKIN	Digital_IO	Signal terminal EXTCLKIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EXTCLKIN. Supported peripheral buses: General.
14	INT/EXT	Digital_IO	Signal terminal INT/EXT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT/EXT. Supported peripheral buses: General.

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